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| author | John David Anglin <dave.anglin@nrc-cnrc.gc.ca> | 2003-11-11 16:16:41 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2003-11-11 16:16:41 +0000 |
| commit | 4d595e43423f86afa558ee8238d37c64ad6b475e (patch) | |
| tree | a7167580cbc3185eda9d5ef583b08b32e173d98c | |
| parent | 5237cd77c28ff1bcfddc6ef7029038bd747bea4c (diff) | |
| download | gcc-4d595e43423f86afa558ee8238d37c64ad6b475e.zip gcc-4d595e43423f86afa558ee8238d37c64ad6b475e.tar.gz gcc-4d595e43423f86afa558ee8238d37c64ad6b475e.tar.bz2 | |
pa.h (TRAMPOLINE_TEMPLATE): Fix flushing of cache lines when generating 64-bit code.
* pa.h (TRAMPOLINE_TEMPLATE): Fix flushing of cache lines when
generating 64-bit code.
From-SVN: r73451
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/pa/pa.h | 17 |
2 files changed, 14 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d63e675..b7fa480 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2003-11-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * pa.h (TRAMPOLINE_TEMPLATE): Fix flushing of cache lines when + generating 64-bit code. + 2003-11-10 David Edelsohn <edelsohn@gnu.org> * config/rs6000/rs6000.c (legitimate_lo_sum_address_p): Remove diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 37d3653..ab15e79 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -993,7 +993,7 @@ extern int may_call_alloca; #define TRAMPOLINE_TEMPLATE(FILE) \ { \ - if (! TARGET_64BIT) \ + if (!TARGET_64BIT) \ { \ fputs ("\tldw 36(%r22),%r21\n", FILE); \ fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \ @@ -1052,7 +1052,7 @@ extern int may_call_alloca; #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ { \ - if (! TARGET_64BIT) \ + if (!TARGET_64BIT) \ { \ rtx start_addr, end_addr; \ \ @@ -1070,9 +1070,9 @@ extern int may_call_alloca; start_addr = force_reg (Pmode, (TRAMP)); \ end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \ emit_insn (gen_dcacheflush (start_addr, end_addr)); \ - end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \ emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \ - gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\ + gen_reg_rtx (Pmode), \ + gen_reg_rtx (Pmode))); \ } \ else \ { \ @@ -1090,13 +1090,14 @@ extern int may_call_alloca; start_addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \ emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \ /* fdc and fic only use registers for the address to flush, \ - they do not accept integer displacements. */ \ + they do not accept integer displacements. PA 2.0 cache \ + lines are 64 bytes. */ \ start_addr = force_reg (Pmode, (TRAMP)); \ - end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \ + end_addr = force_reg (Pmode, plus_constant ((TRAMP), 64)); \ emit_insn (gen_dcacheflush (start_addr, end_addr)); \ - end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \ emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \ - gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\ + gen_reg_rtx (Pmode), \ + gen_reg_rtx (Pmode))); \ } \ } |