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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-05-24 15:03:47 +0200 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-06-14 13:35:49 +0200 |
commit | 4bf0dcb0492c40be7e0603b13a8b5949609388dd (patch) | |
tree | 91e6e0202c1f56ae5cc23a79882b3878b00b89af | |
parent | e07a876c07601e1f3a27420f7d055d20193c362c (diff) | |
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RISC-V: add consecutive_bits_operand predicate
Provide an easy way to constrain for constants that are a a single,
consecutive run of ones.
gcc/ChangeLog:
* config/riscv/predicates.md (consecutive_bits_operand):
Implement new predicate.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
-rw-r--r-- | gcc/config/riscv/predicates.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index c37caa2..90db5df 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -243,3 +243,14 @@ (define_predicate "imm5_operand" (and (match_code "const_int") (match_test "INTVAL (op) < 5"))) + +;; A CONST_INT operand that consists of a single run of consecutive set bits. +(define_predicate "consecutive_bits_operand" + (match_code "const_int") +{ + unsigned HOST_WIDE_INT val = UINTVAL (op); + if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) + return false; + + return true; +}) |