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| author | YunQiang Su <syq@gcc.gnu.org> | 2024-05-29 02:28:25 +0800 |
|---|---|---|
| committer | YunQiang Su <syq@gcc.gnu.org> | 2024-05-30 09:48:08 +0800 |
| commit | 201cfa725587d13867b4dc25955434ebe90aff7b (patch) | |
| tree | e4741d621e1a9b847d68c92703b7bed4adb894cd | |
| parent | 8f6c56cda5b451e48913b73482c4129a9b6be46d (diff) | |
| download | gcc-201cfa725587d13867b4dc25955434ebe90aff7b.zip gcc-201cfa725587d13867b4dc25955434ebe90aff7b.tar.gz gcc-201cfa725587d13867b4dc25955434ebe90aff7b.tar.bz2 | |
MIPS16: Mark $2/$3 as clobbered if GP is used
PR Target/84790.
The gp init sequence
li $2,%hi(_gp_disp)
addiu $3,$pc,%lo(_gp_disp)
sll $2,16
addu $2,$3
is generated directly in `mips_output_function_prologue`, and does
not appear in the RTL.
So the IRA/IPA passes are not aware that $2/$3 have been clobbered,
so they may be used for cross (local) function call.
Let's mark $2/$3 clobber both:
- Just after the UNSPEC_GP RTL of a function;
- Just after a function call.
Reported-by: Matthias Schiffer <mschiffer@universe-factory.net>
Origin-Patch-by: Felix Fietkau <nbd@nbd.name>.
gcc
* config/mips/mips.cc(mips16_gp_pseudo_reg): Mark
MIPS16_PIC_TEMP and MIPS_PROLOGUE_TEMP clobbered.
(mips_emit_call_insn): Mark MIPS16_PIC_TEMP and
MIPS_PROLOGUE_TEMP clobbered if MIPS16 and CALL_CLOBBERED_GP.
(cherry picked from commit 915440eed21de367cb41857afb5273aff5bcb737)
| -rw-r--r-- | gcc/config/mips/mips.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index ce764a5..1156d21 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -3233,6 +3233,9 @@ mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) { rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg); + clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); + clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), + MIPS_PROLOGUE_TEMP (word_mode)); } return insn; @@ -3329,7 +3332,13 @@ mips16_gp_pseudo_reg (void) rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); rtx_insn *insn = emit_insn_after (set, scan); INSN_LOCATION (insn) = 0; - + /* NewABI support hasn't been implement. NewABI should generate RTL + sequence instead of ASM sequence directly. */ + if (mips_current_loadgp_style () == LOADGP_OLDABI) + { + emit_clobber (MIPS16_PIC_TEMP); + emit_clobber (MIPS_PROLOGUE_TEMP (Pmode)); + } pop_topmost_sequence (); } |