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| author | Jakub Jelinek <jakub@redhat.com> | 2024-06-04 12:20:13 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2024-06-04 16:19:18 +0200 |
| commit | 1c1bc2553f6cb6d104f1f1b749aac0f39c4a3959 (patch) | |
| tree | 1f1a50ef21a1c1d4a54dd73dec6231e419d0a3e5 | |
| parent | a7dd44c02ec1047166b4bacc3faa6255c816da2a (diff) | |
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invoke.texi: Clarify -march=lujiazui
I was recently searching which exact CPUs are affected by the PR114576
wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived
at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march=
cases which do enable -maes and don't enable -mavx).
But when double-checking that against the invoke.texi documentation,
that was true for the first 3, but lujiazui said it supported AVX.
I was really confused by that, until I found the
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html
explanation. So, seems the CPUs do have AVX and F16C but -march=lujiazui
doesn't enable those and even activelly attempts to filter those out from
the announced CPUID features, in glibc as well as e.g. in libgcc.
Thus, I think we should document what actually happens, otherwise
users could assume that
gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't.
2024-06-04 Jakub Jelinek <jakub@redhat.com>
* doc/invoke.texi (lujiazui): Clarify that while the CPUs do support
AVX and F16C, -march=lujiazui actually doesn't enable those.
(cherry picked from commit 09b4ab53155ea16e1fb12c2afcd9b6fe29a31c74)
| -rw-r--r-- | gcc/doc/invoke.texi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9456ced..a916d61 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -34732,8 +34732,10 @@ instruction set support. @item lujiazui ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} +for performance reasons. @item yongfeng ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, |