diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2014-04-17 21:50:58 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2014-04-17 21:50:58 +0000 |
| commit | fe799eeaff39cdf075769cbf99cd8d668f0d37fe (patch) | |
| tree | 992126f1cf22ed42c3a76db74e74cce8d2739402 | |
| parent | e85baec793f3560bdace25d061dd05874ff5cd2f (diff) | |
| download | gcc-fe799eeaff39cdf075769cbf99cd8d668f0d37fe.zip gcc-fe799eeaff39cdf075769cbf99cd8d668f0d37fe.tar.gz gcc-fe799eeaff39cdf075769cbf99cd8d668f0d37fe.tar.bz2 | |
re PR target/60876 (2014-04-17 change to machmode.h breaks PowerPC)
2014-04-17 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60876
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Make sure
GET_MODE_SIZE gets passed an enum machine_mode type and not
integer.
(rs6000_init_hard_regno_mode_ok): Likewise.
From-SVN: r209498
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 17 |
2 files changed, 18 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b9874c0..4c15285 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-04-17 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/60876 + * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Make sure + GET_MODE_SIZE gets passed an enum machine_mode type and not + integer. + (rs6000_init_hard_regno_mode_ok): Likewise. + 2014-04-17 Jan Hubicka <hubicka@ucw.cz> * ipa-inline.c (inline_small_functions): Account only non-cold diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 494efc5..f431e73 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2329,6 +2329,8 @@ rs6000_setup_reg_addr_masks (void) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; + /* SDmode is special in that we want to access it only via REG+REG addressing on power7 and above, since we want to use the LFIWZX and STFIWZX instructions to load it. */ @@ -2363,13 +2365,13 @@ rs6000_setup_reg_addr_masks (void) if (TARGET_UPDATE && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) - && GET_MODE_SIZE (m) <= 8 - && !VECTOR_MODE_P (m) - && !COMPLEX_MODE_P (m) + && GET_MODE_SIZE (m2) <= 8 + && !VECTOR_MODE_P (m2) + && !COMPLEX_MODE_P (m2) && !indexed_only_p - && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8) - && !(m == DFmode && TARGET_UPPER_REGS_DF) - && !(m == SFmode && TARGET_UPPER_REGS_SF)) + && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8) + && !(m2 == DFmode && TARGET_UPPER_REGS_DF) + && !(m2 == SFmode && TARGET_UPPER_REGS_SF)) { addr_mask |= RELOAD_REG_PRE_INCDEC; @@ -2815,6 +2817,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; int reg_size2 = reg_size; /* TFmode/TDmode always takes 2 registers, even in VSX. */ @@ -2823,7 +2826,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_size2 = UNITS_PER_FP_WORD; rs6000_class_max_nregs[m][c] - = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2; + = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2; } } |