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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:07:04 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:07:04 -0700 |
| commit | 3fdce4b1ef47f305cd90e62905b4adc8a13a73c5 (patch) | |
| tree | 23a0b96d6f4cbed6e46cc2c64e7c818a13bc1d64 | |
| parent | 08266db93f51f2bf4fe3a211c2f9f4bf1875f725 (diff) | |
| download | gcc-3fdce4b1ef47f305cd90e62905b4adc8a13a73c5.zip gcc-3fdce4b1ef47f305cd90e62905b4adc8a13a73c5.tar.gz gcc-3fdce4b1ef47f305cd90e62905b4adc8a13a73c5.tar.bz2 | |
i386: Emulate MMX smulv4hi3_highpart with SSE
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
From-SVN: r271219
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 25 |
2 files changed, 23 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index db75ab4..7b2a9bb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,14 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow + TARGET_MMX_WITH_SSE. + (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add + SSE support. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. (mulv4hi3): New. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b51f3ac..d7c3bd4 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -773,27 +773,32 @@ (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 16))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 16))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmulhw\t{%2, %0|%0, %2} + pmulhw\t{%2, %0|%0, %2} + vpmulhw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_umulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand") |