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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:10:32 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:10:32 -0700 |
| commit | 2629da835003ae3ca3f39a4888fa447fe966b011 (patch) | |
| tree | bbb6a0d3f51bfd5e3b7c3a1d02cb4794b1de3786 | |
| parent | df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d (diff) | |
| download | gcc-2629da835003ae3ca3f39a4888fa447fe966b011.zip gcc-2629da835003ae3ca3f39a4888fa447fe966b011.tar.gz gcc-2629da835003ae3ca3f39a4888fa447fe966b011.tar.bz2 | |
i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE
Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq<mode>3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq<mode>3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt<mode>3): Likewise.
From-SVN: r271224
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 43 |
2 files changed, 35 insertions, 17 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 12ab4d0..856ff3c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,15 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_eq<mode>3): Also allow + TARGET_MMX_WITH_SSE. + (*mmx_eq<mode>3): Also allow TARGET_MMX_WITH_SSE. Add SSE + support. + (mmx_gt<mode>3): Likewise. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_andnot<mode>3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d3201d8..c1f0b0c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1042,30 +1042,39 @@ (define_expand "mmx_eq<mode>3" [(set (match_operand:MMXMODEI 0 "register_operand") (eq:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand") - (match_operand:MMXMODEI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODEI 1 "register_mmxmem_operand") + (match_operand:MMXMODEI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") (define_insn "*mmx_eq<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (eq:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" - "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcmp") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" + "@ + pcmpeq<mmxvecsize>\t{%2, %0|%0, %2} + pcmpeq<mmxvecsize>\t{%2, %0|%0, %2} + vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcmp,ssecmp,ssecmp") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_gt<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (gt:MMXMODEI - (match_operand:MMXMODEI 1 "register_operand" "0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcmp") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + pcmpgt<mmxvecsize>\t{%2, %0|%0, %2} + pcmpgt<mmxvecsize>\t{%2, %0|%0, %2} + vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcmp,ssecmp,ssecmp") + (set_attr "mode" "DI,TI,TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; |