diff options
author | Cupertino Miranda <cupertino.miranda@oracle.com> | 2024-03-20 19:06:47 +0000 |
---|---|---|
committer | Cupertino Miranda <cupertino.miranda@oracle.com> | 2024-04-19 11:09:16 +0100 |
commit | d7190d0b9a8e395f46b475e4d525f2b6a0ce4df4 (patch) | |
tree | 2d63a754dd513f577b494ac89fe7322f851fb7c8 | |
parent | 4d4929fe0654d51b52a2bf6e6188d7aad0bf17ac (diff) | |
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bpf: support more instructions to match CO-RE relocations
BPF supports multiple instructions to be CO-RE relocatable regardless of
the position of the immediate field in the encoding.
In particular, not only the MOV instruction allows a CO-RE
relocation of its immediate operand, but the LD and ST instructions can
have a CO-RE relocation happening to their offset immediate operand,
even though those operands are encoded in different encoding bits.
This patch moves matching from a more traditional matching of the
UNSPEC_CORE_RELOC pattern within a define_insn to a match within the
constraints of both immediates and address operands from more generic
mov define_insn rule.
gcc/Changelog:
* config/bpf/bpf-protos.h (bpf_add_core_reloc): Renamed function
to bpf_output_move.
* config/bpf/bpf.cc (bpf_legitimate_address_p): Allow
UNSPEC_CORE_RELOC to match an address.
(bpf_insn_cost): Make UNSPEC_CORE_RELOC immediate moves
expensive to prioritize loads and stores.
(TARGET_INSN_COST): Add hook.
(bpf_output_move): Wrapper to call bpf_output_core_reloc.
(bpf_print_operand): Add support to print immediate operands
specified with the UNSPEC_CORE_RELOC.
(bpf_print_operand_address): Likewise, but to support
UNSPEC_CORE_RELOC in addresses.
(bpf_init_builtins): Flag BPF_BUILTIN_CORE_RELOC as NOTHROW.
* config/bpf/bpf.md: Wrap patterns for MOV, LD and ST
instruction with bpf_output_move call.
(mov_reloc_core<MM:mode>): Remove now spurious define_insn.
* config/bpf/constraints.md: Added "c" and "C" constraints to
match immediates represented with UNSPEC_CORE_RELOC.
* config/bpf/core-builtins.cc (bpf_add_core_reloc): Remove
(bpf_output_core_reloc): Add function to create the CO-RE
relocations based on new matching rules.
* config/bpf/core-builtins.h (bpf_output_core_reloc): Add
prototype.
* config/bpf/predicates.md (core_imm_operand) Add predicate.
(mov_src_operand): Add match for core_imm_operand.
gcc/testsuite/ChangeLog:
* gcc.target/bpf/btfext-funcinfo.c: Updated to changes.
* gcc.target/bpf/core-builtin-fieldinfo-const-elimination.c:
Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-existence-1.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-sign-1.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-sign-2.c: Likewise.
* gcc.target/bpf/core-builtin-fieldinfo-size-1.c: Likewise.
19 files changed, 189 insertions, 91 deletions
diff --git a/gcc/config/bpf/bpf-protos.h b/gcc/config/bpf/bpf-protos.h index ac0c2f4..b4866d3 100644 --- a/gcc/config/bpf/bpf-protos.h +++ b/gcc/config/bpf/bpf-protos.h @@ -30,7 +30,7 @@ extern void bpf_print_operand_address (FILE *, rtx); extern void bpf_expand_prologue (void); extern void bpf_expand_epilogue (void); extern void bpf_expand_cbranch (machine_mode, rtx *); -const char *bpf_add_core_reloc (rtx *operands, const char *templ); +const char *bpf_output_move (rtx *operands, const char *templ); class gimple_opt_pass; gimple_opt_pass *make_pass_lower_bpf_core (gcc::context *ctxt); diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index fb60770..d9141dd 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -584,6 +584,16 @@ bpf_legitimate_address_p (machine_mode mode, if (bpf_address_base_p (x0, strict) && GET_CODE (x1) == CONST_INT) return IN_RANGE (INTVAL (x1), -1 - 0x7fff, 0x7fff); + /* Check if any of the PLUS operation operands is a CORE unspec, and at + least the local value for the offset fits in the 16 bits available + in the encoding. */ + if (bpf_address_base_p (x1, strict) + && GET_CODE (x0) == UNSPEC && XINT (x0, 1) == UNSPEC_CORE_RELOC) + return IN_RANGE (INTVAL (XVECEXP (x0, 0, 0)), -1 - 0x7fff, 0x7fff); + if (bpf_address_base_p (x0, strict) + && GET_CODE (x1) == UNSPEC && XINT (x1, 1) == UNSPEC_CORE_RELOC) + return IN_RANGE (INTVAL (XVECEXP (x1, 0, 0)), -1 - 0x7fff, 0x7fff); + break; } default: @@ -615,6 +625,21 @@ bpf_rtx_costs (rtx x ATTRIBUTE_UNUSED, #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS bpf_rtx_costs +static int +bpf_insn_cost (rtx_insn *insn, bool speed ATTRIBUTE_UNUSED) +{ + rtx pat = PATTERN (insn); + if(GET_CODE (pat) == SET + && GET_CODE (XEXP (pat, 1)) == UNSPEC + && XINT (XEXP (pat, 1), 1) == UNSPEC_CORE_RELOC) + return COSTS_N_INSNS (100); + + return COSTS_N_INSNS (1); +} + +#undef TARGET_INSN_COST +#define TARGET_INSN_COST bpf_insn_cost + /* Return true if an argument at the position indicated by CUM should be passed by reference. If the hook returns true, a copy of that argument is made in memory and a pointer to the argument is passed @@ -771,6 +796,13 @@ bpf_output_call (rtx target) return ""; } +const char * +bpf_output_move (rtx *operands, const char *templ) +{ + bpf_output_core_reloc (operands, 2); + return templ; +} + /* Print register name according to assembly dialect. In normal syntax registers are printed like %rN where N is the register number. @@ -852,6 +884,12 @@ bpf_print_operand (FILE *file, rtx op, int code) gcc_unreachable (); } break; + case UNSPEC: + if (XINT (op, 1) == UNSPEC_CORE_RELOC) + bpf_print_operand (file, XVECEXP (op, 0, 0), code); + else + gcc_unreachable (); + break; default: output_addr_const (file, op); } @@ -880,13 +918,24 @@ bpf_print_operand_address (FILE *file, rtx addr) rtx op0 = XEXP (addr, 0); rtx op1 = XEXP (addr, 1); - if (GET_CODE (op0) == REG && GET_CODE (op1) == CONST_INT) + if (GET_CODE (op1) == REG) { + op0 = op1; + op1 = XEXP (addr, 0); + } + + if (GET_CODE (op0) == REG + && (GET_CODE (op1) == CONST_INT + || (GET_CODE (op1) == UNSPEC + && XINT (op1, 1) == UNSPEC_CORE_RELOC))) { if (asm_dialect == ASM_NORMAL) fprintf (file, "["); bpf_print_register (file, op0, 0); fprintf (file, "+"); - output_addr_const (file, op1); + if (GET_CODE (op1) == UNSPEC) + output_addr_const (file, XVECEXP (op1, 0, 0)); + else + output_addr_const (file, op1); if (asm_dialect == ASM_NORMAL) fprintf (file, "]"); } @@ -962,6 +1011,7 @@ bpf_init_builtins (void) build_function_type_list (integer_type_node,integer_type_node, 0)); DECL_PURE_P (bpf_builtins[BPF_BUILTIN_CORE_RELOC]) = 1; + TREE_NOTHROW (bpf_builtins[BPF_BUILTIN_CORE_RELOC]) = 1; bpf_init_core_builtins (); } diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index ea688aa..9585932 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -281,8 +281,8 @@ "" "@ {and\t%0,0xffff|%0 &= 0xffff} - {mov\t%0,%1\;and\t%0,0xffff|%0 = %1;%0 &= 0xffff} - {ldxh\t%0,%1|%0 = *(u16 *) (%1)}" + *return bpf_output_move (operands, \"{mov\t%0,%1\;and\t%0,0xffff|%0 = %1;%0 &= 0xffff}\"); + *return bpf_output_move (operands, \"{ldxh\t%0,%1|%0 = *(u16 *) (%1)}\");" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendqidi2" @@ -291,8 +291,8 @@ "" "@ {and\t%0,0xff|%0 &= 0xff} - {mov\t%0,%1\;and\t%0,0xff|%0 = %1;%0 &= 0xff} - {ldxb\t%0,%1|%0 = *(u8 *) (%1)}" + *return bpf_output_move (operands, \"{mov\t%0,%1\;and\t%0,0xff|%0 = %1;%0 &= 0xff}\"); + *return bpf_output_move (operands, \"{ldxb\t%0,%1|%0 = *(u8 *) (%1)}\");" [(set_attr "type" "alu,alu,ldx")]) (define_insn "zero_extendsidi2" @@ -301,8 +301,8 @@ (match_operand:SI 1 "nonimmediate_operand" "r,q")))] "" "@ - * return bpf_has_alu32 ? \"{mov32\t%0,%1|%0 = %1}\" : \"{mov\t%0,%1\;and\t%0,0xffffffff|%0 = %1;%0 &= 0xffffffff}\"; - {ldxw\t%0,%1|%0 = *(u32 *) (%1)}" + *return bpf_output_move (operands, bpf_has_alu32 ? \"{mov32\t%0,%1|%0 = %1}\" : \"{mov\t%0,%1\;and\t%0,0xffffffff|%0 = %1;%0 &= 0xffffffff}\"); + *return bpf_output_move (operands, \"{ldxw\t%0,%1|%0 = *(u32 *) (%1)}\");" [(set_attr "type" "alu,ldx")]) ;;; Sign-extension @@ -328,8 +328,8 @@ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,q")))] "bpf_has_smov" "@ - {movs\t%0,%1,32|%0 = (s32) %1} - {ldxsw\t%0,%1|%0 = *(s32 *) (%1)}" + *return bpf_output_move (operands, \"{movs\t%0,%1,32|%0 = (s32) %1}\"); + *return bpf_output_move (operands, \"{ldxsw\t%0,%1|%0 = *(s32 *) (%1)}\");" [(set_attr "type" "alu,ldx")]) (define_insn "extendhidi2" @@ -337,8 +337,8 @@ (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,q")))] "bpf_has_smov" "@ - {movs\t%0,%1,16|%0 = (s16) %1} - {ldxsh\t%0,%1|%0 = *(s16 *) (%1)}" + *return bpf_output_move (operands, \"{movs\t%0,%1,16|%0 = (s16) %1}\"); + *return bpf_output_move (operands, \"{ldxsh\t%0,%1|%0 = *(s16 *) (%1)}\");" [(set_attr "type" "alu,ldx")]) (define_insn "extendqidi2" @@ -346,22 +346,22 @@ (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,q")))] "bpf_has_smov" "@ - {movs\t%0,%1,8|%0 = (s8) %1} - {ldxsb\t%0,%1|%0 = *(s8 *) (%1)}" + *return bpf_output_move (operands, \"{movs\t%0,%1,8|%0 = (s8) %1}\"); + *return bpf_output_move (operands, \"{ldxsb\t%0,%1|%0 = *(s8 *) (%1)}\");" [(set_attr "type" "alu,ldx")]) (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] "bpf_has_smov" - "{movs32\t%0,%1,16|%w0 = (s16) %w1}" + "*return bpf_output_move (operands, \"{movs32\t%0,%1,16|%w0 = (s16) %w1}\");" [(set_attr "type" "alu")]) (define_insn "extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))] "bpf_has_smov" - "{movs32\t%0,%1,8|%w0 = (s8) %w1}" + "*return bpf_output_move (operands, \"{movs32\t%0,%1,8|%w0 = (s8) %w1}\");" [(set_attr "type" "alu")]) ;;;; Data movement @@ -380,31 +380,17 @@ }") (define_insn "*mov<MM:mode>" - [(set (match_operand:MM 0 "nonimmediate_operand" "=r, r,r,q,q") - (match_operand:MM 1 "mov_src_operand" " q,rI,B,r,I"))] + [(set (match_operand:MM 0 "nonimmediate_operand" "=r, r, r,q,q") + (match_operand:MM 1 "mov_src_operand" " q,rIc,BC,r,I"))] "" "@ - {ldx<mop>\t%0,%1|%0 = *(<smop> *) (%1)} - {mov\t%0,%1|%0 = %1} - {lddw\t%0,%1|%0 = %1 ll} - {stx<mop>\t%0,%1|*(<smop> *) (%0) = %1} - {st<mop>\t%0,%1|*(<smop> *) (%0) = %1}" + *return bpf_output_move (operands, \"{ldx<mop>\t%0,%1|%0 = *(<smop> *) (%1)}\"); + *return bpf_output_move (operands, \"{mov\t%0,%1|%0 = %1}\"); + *return bpf_output_move (operands, \"{lddw\t%0,%1|%0 = %1 ll}\"); + *return bpf_output_move (operands, \"{stx<mop>\t%0,%1|*(<smop> *) (%0) = %1}\"); + *return bpf_output_move (operands, \"{st<mop>\t%0,%1|*(<smop> *) (%0) = %1}\");" [(set_attr "type" "ldx,alu,alu,stx,st")]) -(define_insn "*mov_reloc_core<MM:mode>" - [(set (match_operand:MM 0 "nonimmediate_operand" "=r,q,r") - (unspec:MM [ - (match_operand:MM 1 "immediate_operand" " I,I,B") - (match_operand:SI 2 "immediate_operand" " I,I,I") - ] UNSPEC_CORE_RELOC) - )] - "" - "@ - *return bpf_add_core_reloc (operands, \"{mov\t%0,%1|%0 = %1}\"); - *return bpf_add_core_reloc (operands, \"{st<mop>\t%0,%1|*(<smop> *) (%0) = %1}\"); - *return bpf_add_core_reloc (operands, \"{lddw\t%0,%1|%0 = %1 ll}\");" - [(set_attr "type" "alu,st,alu")]) - ;;;; Shifts (define_mode_iterator SIM [(SI "bpf_has_alu32") DI]) diff --git a/gcc/config/bpf/constraints.md b/gcc/config/bpf/constraints.md index 4b8d658..dd04e67 100644 --- a/gcc/config/bpf/constraints.md +++ b/gcc/config/bpf/constraints.md @@ -34,6 +34,26 @@ "Register r0") ;; +;; BPF CO-RE immediate constraints. +;; This constraints are used to match with the immediate operand that is +;; represented with an UNSPEC_CORE_RELOC. This unspec is the result of using the +;; BPF CO-RE infrastructure. +;; It differentiates from a normal immediate constraints, as the instruction +;; will also emit a BTF based specific relocation, i.e. a CO-RE relocation. +;; + +(define_constraint "c" + "A 32-bit CO-RE signed immediate." + (and (match_code "unspec") + (match_test "XINT (op, 1) == UNSPEC_CORE_RELOC") + (match_test "IN_RANGE (XVECEXP (op, 0, 0), -1 - 0x7fffffff, 0x7fffffff)"))) + +(define_constraint "C" + "For 64-bit CO-RE signed immediate." + (and (match_code "unspec") + (match_test "XINT (op, 1) == UNSPEC_CORE_RELOC"))) + +;; ;; Memory constraints. ;; diff --git a/gcc/config/bpf/core-builtins.cc b/gcc/config/bpf/core-builtins.cc index 8333ad8..e03e986 100644 --- a/gcc/config/bpf/core-builtins.cc +++ b/gcc/config/bpf/core-builtins.cc @@ -1561,6 +1561,7 @@ bpf_expand_core_builtin (tree exp, enum bpf_builtins code) return NULL_RTX; } + /* This function is called in the final assembly output for the unspec:UNSPEC_CORE_RELOC. It recovers the vec index kept as the third operand and collects the data from the vec. With that it calls the process @@ -1568,27 +1569,63 @@ bpf_expand_core_builtin (tree exp, enum bpf_builtins code) Also it creates a label pointing to the unspec instruction and uses it in the CO-RE relocation creation. */ -const char * -bpf_add_core_reloc (rtx *operands, const char *templ) +void +bpf_output_core_reloc (rtx *operands, int nr_ops) { - struct cr_builtins *data = get_builtin_data (INTVAL (operands[2])); - builtin_helpers helper; - helper = core_builtin_helpers[data->orig_builtin_code]; - - rtx_code_label * tmp_label = gen_label_rtx (); - output_asm_label (tmp_label); - assemble_name (asm_out_file, ":\n"); + /* Search for an UNSPEC_CORE_RELOC within the operands of the emitting + intructions. */ + rtx unspec_exp = NULL_RTX; + for (int i = 0; i < nr_ops; i++) + { + rtx op = operands[i]; - gcc_assert (helper.process != NULL); - struct cr_final reloc_data = helper.process (data); - make_core_relo (&reloc_data, tmp_label); + /* An immediate CO-RE reloc. */ + if (GET_CODE (op) == UNSPEC + && XINT (op, 1) == UNSPEC_CORE_RELOC) + unspec_exp = op; - /* Replace default value for later processing builtin types. - Example if the type id builtins. */ - if (data->rtx_default_value != NULL_RTX) - operands[1] = data->rtx_default_value; + /* In case of a MEM operation with an offset resolved in CO-RE. */ + if (GET_CODE (op) == MEM + && (op = XEXP (op, 0)) != NULL_RTX + && (GET_CODE (op) == PLUS)) + { + rtx x0 = XEXP (op, 0); + rtx x1 = XEXP (op, 1); + + if (GET_CODE (x0) == UNSPEC + && XINT (x0, 1) == UNSPEC_CORE_RELOC) + unspec_exp = x0; + if (GET_CODE (x1) == UNSPEC + && XINT (x1, 1) == UNSPEC_CORE_RELOC) + unspec_exp = x1; + } + if (unspec_exp != NULL_RTX) + break; + } - return templ; + if (unspec_exp != NULL_RTX) + { + int index = INTVAL (XVECEXP (unspec_exp, 0, 1)); + struct cr_builtins *data = get_builtin_data (index); + builtin_helpers helper; + helper = core_builtin_helpers[data->orig_builtin_code]; + + rtx_code_label * tmp_label = gen_label_rtx (); + output_asm_label (tmp_label); + assemble_name (asm_out_file, ":\n"); + + rtx orig_default_value = data->rtx_default_value; + + gcc_assert (helper.process != NULL); + struct cr_final reloc_data = helper.process (data); + make_core_relo (&reloc_data, tmp_label); + + /* Replace default value for later processing builtin types. + An example are the type id builtins. */ + if (data->rtx_default_value != NULL_RTX + && orig_default_value != data->rtx_default_value) + XVECEXP (unspec_exp, 0, 0) = data->rtx_default_value; + } } static tree diff --git a/gcc/config/bpf/core-builtins.h b/gcc/config/bpf/core-builtins.h index e56b55b..ebe321b 100644 --- a/gcc/config/bpf/core-builtins.h +++ b/gcc/config/bpf/core-builtins.h @@ -59,5 +59,7 @@ void bpf_init_core_builtins (void); rtx bpf_expand_core_builtin (tree exp, enum bpf_builtins code); tree bpf_resolve_overloaded_core_builtin (location_t loc, tree fndecl, void *arglist); +void +bpf_output_core_reloc (rtx *operands, int nr_ops); #endif diff --git a/gcc/config/bpf/predicates.md b/gcc/config/bpf/predicates.md index fa04258..568156f 100644 --- a/gcc/config/bpf/predicates.md +++ b/gcc/config/bpf/predicates.md @@ -27,6 +27,10 @@ (match_test "IN_RANGE (INTVAL (op), 0, 0xffffffff)")) (match_code "symbol_ref,label_ref,const"))) +(define_predicate "core_imm_operand" + (and (match_code "unspec") + (match_test "XINT (op, 1) == UNSPEC_CORE_RELOC"))) + (define_predicate "lddw_operand" (match_code "symbol_ref,label_ref,const,const_double,const_int")) @@ -57,7 +61,8 @@ (define_predicate "mov_src_operand" (ior (match_operand 0 "memory_operand") (match_operand 0 "reg_or_imm_operand") - (match_operand 0 "lddw_operand"))) + (match_operand 0 "lddw_operand") + (match_operand 0 "core_imm_operand"))) (define_predicate "register_compare_operator" (match_code "eq,ne,geu,gtu,ge,gt")) diff --git a/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c index a59c5bd..6fdd145 100644 --- a/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c +++ b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c @@ -35,8 +35,6 @@ int bar_func (struct T *t) /* { dg-final { scan-assembler-times "label for function foo_func" 1 } } */ /* { dg-final { scan-assembler-times "label for function bar_func" 1 } } */ -/* { dg-final { scan-assembler-times "ascii \"0:2:1:1:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ -/* { dg-final { scan-assembler-times "ascii \"0:2:1:2.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"foo_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"bar_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "FuncInfo entry size" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-const-elimination.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-const-elimination.c index 5f83548..51e938c 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-const-elimination.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-const-elimination.c @@ -25,5 +25,5 @@ unsigned int foo (struct T *t) return __builtin_preserve_field_info (t->s[0].a1, FIELD_BYTE_OFFSET) + 1; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],4" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],4" 1 } } */ /* { dg-final { scan-assembler-times "\[\t \]add32\[\t \]%r\[0-9\],1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-existence-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-existence-1.c index c55f21a..96119da 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-existence-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-existence-1.c @@ -24,7 +24,7 @@ unsigned int foo (struct S *s) return c + d + u + ar; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],1" 4 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],1" 4 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c index dabf73d..579bc76 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-be.c @@ -24,10 +24,10 @@ unsigned int foo (struct S *s) return x1 + x2 + x3 + x4; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],32" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],38" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],41" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],48" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],32" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],38" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],41" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],48" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c index 99e3982..d48f01a 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-1-le.c @@ -24,10 +24,10 @@ unsigned int foo (struct S *s) return x1 + x2 + x3 + x4; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],58" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],55" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],48" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],32" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],58" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],55" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],48" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],32" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c index 25be969..653ddf6 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-lshift-2.c @@ -26,9 +26,9 @@ unsigned int foo (union U *u) return s0s + s1c + ll; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],48" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],56" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],0" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],48" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],56" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],0" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0:0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0:1:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c index 8b1d8b0..a0ddda8 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c @@ -46,12 +46,12 @@ unsigned int foo (struct T *t) return s0a1 + s0a4 + s0x + s1a1 + s1a4 + s1x + c + d + e1 + e2 + f1; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],4" 2 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],8" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],12" 3 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],16" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],20" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],21" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],4" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],8" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],12" 3 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],16" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],20" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],21" 2 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c index d0c75d9..4776783 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-1.c @@ -23,10 +23,10 @@ unsigned int foo (struct S *s) return x1 + x2 + x3 + x4; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],58" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],61" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],57" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],48" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],58" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],61" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],57" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],48" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c index a71ddc1..a13ff8e 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-rshift-2.c @@ -25,8 +25,8 @@ unsigned int foo (union U *u) return sx + sc + i; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],32" 2 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],56" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],32" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],56" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-1.c index 3b2081e..442ed07 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-1.c @@ -23,8 +23,8 @@ unsigned int foo (struct S *s) return d + u + ar; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],1" 2 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],0" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],1" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],0" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:2.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-2.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-2.c index bf18429..cdc4d4d 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-2.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-sign-2.c @@ -35,8 +35,8 @@ unsigned int foo (union U *u) return i + sig + un; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],1" 2 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],0" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],1" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],0" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-size-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-size-1.c index 8747bde..74707f1 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-size-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-size-1.c @@ -29,10 +29,10 @@ unsigned int foo (union U *u) return ls + s + a2 + a3 + ca; } -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],24" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],20" 1 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],4" 2 } } */ -/* { dg-final { scan-assembler-times "\[\t \]mov\[\t \]%r\[0-9\],15" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],24" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],20" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],4" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]lddw\[\t \]%r\[0-9\],15" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ |