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authorRichard Sandiford <richard.sandiford@arm.com>2019-08-15 08:34:40 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2019-08-15 08:34:40 +0000
commit2ae21bd133c357fcd7b6e06dc7d7d9e0660abe2c (patch)
tree8a597f87da62736b9b03cf048fdaade3f756d26f
parent5e176a613ef2eda92aa65736763a562dc42a50fe (diff)
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[AArch64] Remove unneeded FSUB alternatives and add a new one
The floating-point subtraction patterns don't need to handle subtraction of constants, since those go through the addition patterns instead. There was a missing MOVPRFX alternative for FSUBR though. 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR. From-SVN: r274514
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/aarch64/aarch64-sve.md25
2 files changed, 16 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6bfbd99..62376a5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,9 @@
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
+ FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR.
+
+2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* config/aarch64/aarch64-sve.md (add<SVE_I:mode>3, sub<SVE_I:mode>3)
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index c4e4602..fa7f899 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2878,34 +2878,31 @@
;; ---- [FP] Subtraction
;; -------------------------------------------------------------------------
;; Includes:
-;; - FADD
;; - FSUB
;; - FSUBR
;; -------------------------------------------------------------------------
;; Predicated floating-point subtraction.
(define_insn_and_split "*sub<mode>3"
- [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, w")
+ [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w")
(unspec:SVE_F
- [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
- (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, i, i, Z")
- (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "0, 0, vsA, w")
- (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, 0, w")]
+ [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+ (match_operand:SI 4 "aarch64_sve_gp_strictness" "i, Z, i")
+ (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "vsA, w, vsA")
+ (match_operand:SVE_F 3 "register_operand" "0, w, 0")]
UNSPEC_COND_FSUB))]
- "TARGET_SVE
- && (register_operand (operands[2], <MODE>mode)
- || register_operand (operands[3], <MODE>mode))"
+ "TARGET_SVE"
"@
- fsub\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
- fadd\t%0.<Vetype>, %1/m, %0.<Vetype>, #%N3
fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2
- #"
+ #
+ movprfx\t%0, %3\;fsubr\t%0.<Vetype>, %1/m, %0.<Vetype>, #%2"
; Split the unpredicated form after reload, so that we don't have
; the unnecessary PTRUE.
"&& reload_completed
- && register_operand (operands[2], <MODE>mode)
- && register_operand (operands[3], <MODE>mode)"
+ && register_operand (operands[2], <MODE>mode)"
[(set (match_dup 0) (minus:SVE_F (match_dup 2) (match_dup 3)))]
+ ""
+ [(set_attr "movprfx" "*,*,yes")]
)
;; Predicated floating-point subtraction from a constant, merging with the