[ARM/AArch64][testsuite] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.

2015-01-26  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
	* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
	vXXXhn.inc.

From-SVN: r220117

6 files changed, 140 insertions, 87 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9c526b7..6e099f6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2015-01-26  Christophe Lyon  <christophe.lyon@linaro.org>
+
+	* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
+	* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
+	* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
+	* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
+	* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
+	vXXXhn.inc.
+
 2015-01-26  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/64764
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 0000000..5aabedd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,55 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+  /* Basic test: vec64=vXXXhn(vec128_a, vec128_b), then store the result.  */
+#define TEST_VXXXHN1(INSN, T1, T2, W, W2, N)				\
+  VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+						 VECT_VAR(vector2, T1, W, N)); \
+  vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VXXXHN(INSN, T1, T2, W, W2, N)	\
+  TEST_VXXXHN1(INSN, T1, T2, W, W2, N)
+
+  DECL_VARIABLE_64BITS_VARIANTS(vector64);
+  DECL_VARIABLE_128BITS_VARIANTS(vector1);
+  DECL_VARIABLE_128BITS_VARIANTS(vector2);
+
+  clean_results ();
+
+  /* Fill input vector1 and vector2 with arbitrary values */
+  VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
+  VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
+  VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
+  VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
+  VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
+  VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
+
+  VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
+  VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
+  VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
+  VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
+  VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
+  VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
+
+  TEST_VXXXHN(INSN_NAME, int, s, 16, 8, 8);
+  TEST_VXXXHN(INSN_NAME, int, s, 32, 16, 4);
+  TEST_VXXXHN(INSN_NAME, int, s, 64, 32, 2);
+  TEST_VXXXHN(INSN_NAME, uint, u, 16, 8, 8);
+  TEST_VXXXHN(INSN_NAME, uint, u, 32, 16, 4);
+  TEST_VXXXHN(INSN_NAME, uint, u, 64, 32, 2);
+
+  CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+  CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+  FNNAME (INSN_NAME) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
index 58fd5ea..96ae048 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
@@ -8,100 +8,17 @@
 #include <stdint.h>
 #endif
 
+#define INSN_NAME vaddhn
+#define TEST_MSG "VADDHN"
+
 /* Expected results.  */
 VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32,
 				       0x32, 0x32, 0x32, 0x32 };
 VECT_VAR_DECL(expected,int,16,4) [] = { 0x32, 0x32, 0x32, 0x32 };
 VECT_VAR_DECL(expected,int,32,2) [] = { 0x18, 0x18 };
-VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
 VECT_VAR_DECL(expected,uint,8,8) [] = { 0x3, 0x3, 0x3, 0x3,
 					0x3, 0x3, 0x3, 0x3 };
 VECT_VAR_DECL(expected,uint,16,4) [] = { 0x37, 0x37, 0x37, 0x37 };
 VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3, 0x3 };
-VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
-VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
-					0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
-					0x33, 0x33, 0x33, 0x33,
-					0x33, 0x33, 0x33, 0x33,
-					0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,int,16,8) [] = {  0x3333, 0x3333, 0x3333, 0x3333,
-					 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
-					0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
-					0x3333333333333333 };
-VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
-					 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
-					 0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
-					 0x3333333333333333 };
-VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33,
-					 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
-					 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
-					   0x33333333, 0x33333333 };
-
-#define INSN_NAME vaddhn
-#define TEST_MSG "VADDHN"
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
-  /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result.  */
-#define TEST_VADDHN1(INSN, T1, T2, W, W2, N)				\
-  VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
-						 VECT_VAR(vector2, T1, W, N)); \
-  vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
-
-#define TEST_VADDHN(INSN, T1, T2, W, W2, N)	\
-  TEST_VADDHN1(INSN, T1, T2, W, W2, N)
-
-  DECL_VARIABLE_64BITS_VARIANTS(vector64);
-  DECL_VARIABLE_128BITS_VARIANTS(vector1);
-  DECL_VARIABLE_128BITS_VARIANTS(vector2);
-
-  clean_results ();
-
-  /* Fill input vector1 and vector2 with arbitrary values */
-  VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
-  VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
-  VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
-  VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
-  VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
-  VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
-
-  VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
-  VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
-  VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
-  VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
-  VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
-  VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
-
-  TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
-  TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
-  TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2);
-  TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8);
-  TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4);
-  TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2);
-
-  CHECK_RESULTS (TEST_MSG, "");
-}
 
-int main (void)
-{
-  FNNAME (INSN_NAME) ();
-  return 0;
-}
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
new file mode 100644
index 0000000..12bb3ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vraddhn
+#define TEST_MSG "VRADDHN"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+				       0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4,
+					0x4, 0x4, 0x4, 0x4 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x38, 0x38, 0x38, 0x38 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x4, 0x4 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
new file mode 100644
index 0000000..1ac1b17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vrsubhn
+#define TEST_MSG "VRSUBHN"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+				       0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+					0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
new file mode 100644
index 0000000..acecf41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vsubhn
+#define TEST_MSG "VSUBHN"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+				       0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+					0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+
+#include "vXXXhn.inc"