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author | Uros Bizjak <ubizjak@gmail.com> | 2017-07-18 18:10:20 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-07-18 18:10:20 +0200 |
commit | e822e8858882b88f33a975849c6474031e28ea08 (patch) | |
tree | 53a86e0f124e72940605c760fa9332507f45ee0e | |
parent | 883b0e467ad1e7c9af9131b026b4446d571f3caa (diff) | |
download | gcc-e822e8858882b88f33a975849c6474031e28ea08.zip gcc-e822e8858882b88f33a975849c6474031e28ea08.tar.gz gcc-e822e8858882b88f33a975849c6474031e28ea08.tar.bz2 |
re PR target/81471 (internal compiler error: in curr_insn_transform, at lra-constraints.c:3495)
PR target/81471
* config/i386/i386.md (rorx_immediate_operand): New mode attribute.
(*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as
operand 2 predicate.
(*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as
operand 2 predicate.
(ror,rol -> rorx splitters): Use const_int_operand as
operand 2 predicate.
testsuite/ChangeLog:
PR target/81471
* gcc.target/i386/pr81471.c: New test.
From-SVN: r250315
-rw-r--r-- | gcc/ChangeLog | 11 | ||||
-rw-r--r-- | gcc/config/i386/i386.md | 19 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/i386/pr81471.c | 13 |
4 files changed, 41 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6ffb75..ef0e788 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2017-07-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/81471 + * config/i386/i386.md (rorx_immediate_operand): New mode attribute. + (*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as + operand 2 predicate. + (*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as + operand 2 predicate. + (ror,rol -> rorx splitters): Use const_int_operand as + operand 2 predicate. + 2017-06-18 Richard Biener <rguenther@suse.de> PR tree-optimization/81410 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4018e67..5eff4e4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10732,10 +10732,15 @@ split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]); }) +(define_mode_attr rorx_immediate_operand + [(SI "const_0_to_31_operand") + (DI "const_0_to_63_operand")]) + (define_insn "*bmi2_rorx<mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") - (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (match_operand:QI 2 "immediate_operand" "<S>")))] + (rotatert:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm") + (match_operand:QI 2 "<rorx_immediate_operand>" "<S>")))] "TARGET_BMI2" "rorx\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "rotatex") @@ -10778,7 +10783,7 @@ (define_split [(set (match_operand:SWI48 0 "register_operand") (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") - (match_operand:QI 2 "immediate_operand"))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10792,7 +10797,7 @@ (define_split [(set (match_operand:SWI48 0 "register_operand") (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") - (match_operand:QI 2 "immediate_operand"))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10802,7 +10807,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm") - (match_operand:QI 2 "immediate_operand" "I"))))] + (match_operand:QI 2 "const_0_to_31_operand" "I"))))] "TARGET_64BIT && TARGET_BMI2" "rorx\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "rotatex") @@ -10846,7 +10851,7 @@ [(set (match_operand:DI 0 "register_operand") (zero_extend:DI (rotate:SI (match_operand:SI 1 "nonimmediate_operand") - (match_operand:QI 2 "immediate_operand")))) + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10861,7 +10866,7 @@ [(set (match_operand:DI 0 "register_operand") (zero_extend:DI (rotatert:SI (match_operand:SI 1 "nonimmediate_operand") - (match_operand:QI 2 "immediate_operand")))) + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 80d57b8..1929d15 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-07-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/81471 + * gcc.target/i386/pr81471.c: New test. + 2017-06-18 Richard Biener <rguenther@suse.de> PR tree-optimization/81410 diff --git a/gcc/testsuite/gcc.target/i386/pr81471.c b/gcc/testsuite/gcc.target/i386/pr81471.c new file mode 100644 index 0000000..68b4497 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81471.c @@ -0,0 +1,13 @@ +/* PR target/81471 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mbmi2" } */ + +static inline unsigned int rotl (unsigned int x, int k) +{ + return (x << k) | (x >> (32 - k)); +} + +unsigned long long test (unsigned int z) +{ + return rotl (z, 55); +} |