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| author | Kazu Hirata <kazu@codesourcery.com> | 2006-05-10 17:35:24 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2006-05-10 17:35:24 +0000 |
| commit | e43d8b8a0e28dd561dfafbc829293a262845e05e (patch) | |
| tree | 1a47706b3d025bd053a5fe60442422716590558b | |
| parent | fdafd4613f5e867d6065b9951803279a6d40fa56 (diff) | |
| download | gcc-e43d8b8a0e28dd561dfafbc829293a262845e05e.zip gcc-e43d8b8a0e28dd561dfafbc829293a262845e05e.tar.gz gcc-e43d8b8a0e28dd561dfafbc829293a262845e05e.tar.bz2 | |
re PR target/24949 (FAIL: gcc.c-torture/compile/20000403-2.c -O0)
PR target/24949
* config/m68k/m68k.md (ashrdi_const32, ashrdi_const32_mem,
ashrdi_const, ashrdi3): Use a scratch register.
From-SVN: r113675
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 56 |
2 files changed, 34 insertions, 28 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c52d9dd..e598418 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2006-05-10 Kazu Hirata <kazu@codesourcery.com> + + PR target/24949 + * config/m68k/m68k.md (ashrdi_const32, ashrdi_const32_mem, + ashrdi_const, ashrdi3): Use a scratch register. + 2006-05-10 Richard Guenther <rguenther@suse.de> PR tree-optimization/27302 diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 6bbeff2..8e565a6 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -4283,42 +4283,40 @@ }) (define_insn "ashrdi_const32" - [(set (match_operand:DI 0 "register_operand" "=d") - (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") - (const_int 32)))] - "" -{ - CC_STATUS_INIT; - operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020) - return "move%.l %1,%2\;smi %0\;extb%.l %0"; - else - return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0"; -}) - -(define_insn "ashrdi_const32_mem" - [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<") - (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro") + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,<") + (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro") (const_int 32))) - (clobber (match_scratch:SI 2 "=d,d"))] + (clobber (match_scratch:SI 2 "=X,d,d"))] "" { CC_STATUS_INIT; - if (which_alternative == 1) - operands[3] = operands[0]; - else - operands[3] = adjust_address (operands[0], SImode, 4); - if (TARGET_68020) - return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; + if (which_alternative == 0) + { + operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); + if (TARGET_68020) + return "move%.l %1,%2\;smi %0\;extb%.l %0"; + else + return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0"; + } else - return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; + { + if (which_alternative == 2) + operands[3] = operands[0]; + else if (which_alternative == 1) + operands[3] = adjust_address (operands[0], SImode, 4); + if (TARGET_68020) + return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; + else + return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; + } }) ;; The predicate below must be general_operand, because ashrdi3 allows that (define_insn "ashrdi_const" [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") - (match_operand 2 "const_int_operand" "n")))] + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_scratch:SI 3 "=X"))] "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 @@ -4355,9 +4353,10 @@ }) (define_expand "ashrdi3" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (ashiftrt:DI (match_operand:DI 1 "general_operand" "") - (match_operand 2 "const_int_operand" "")))] + [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") + (ashiftrt:DI (match_operand:DI 1 "general_operand" "") + (match_operand 2 "const_int_operand" ""))) + (clobber (match_scratch:SI 3 ""))])] "!TARGET_COLDFIRE" " { @@ -4368,6 +4367,7 @@ && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) FAIL; + operands[3] = gen_rtx_SCRATCH (SImode); } ") ;; On all 68k models, this makes faster code in a special case. |