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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-01-28 11:45:06 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-01-28 11:45:06 +0000 |
| commit | e2b691c4204110d08206dcc304c9fba56e88b89b (patch) | |
| tree | 9829b46a0efe095f8cc7d52646014d5878b7e17f | |
| parent | f4d7b52072dba04161a95a36f1574820e3339147 (diff) | |
| download | gcc-e2b691c4204110d08206dcc304c9fba56e88b89b.zip gcc-e2b691c4204110d08206dcc304c9fba56e88b89b.tar.gz gcc-e2b691c4204110d08206dcc304c9fba56e88b89b.tar.bz2 | |
Several instructions disassemble a zero immediate as wzr/xzr due to using a register operand in the disassembly.
Several instructions disassemble a zero immediate as wzr/xzr due to
using a register operand in the disassembly. Avoid this by removing
the register operand.
2016-01-28 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.md (ccmp<mode>): Disassemble
immediate as %1.
(add<mode>3_compare0): Likewise.
(addsi3_compare0_uxtw): Likewise.
(add<mode>3nr_compare0): Likewise.
(compare_neg<mode>): Likewise.
(<optab><mode>3): Likewise.
From-SVN: r232921
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
2 files changed, 16 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aa98585..99f2bdb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-01-28 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64.md (ccmp<mode>): Disassemble + immediate as %1. + (add<mode>3_compare0): Likewise. + (addsi3_compare0_uxtw): Likewise. + (add<mode>3nr_compare0): Likewise. + (compare_neg<mode>): Likewise. + (<optab><mode>3): Likewise. + 2016-01-28 Ilya Enkovich <enkovich.gnu@gmail.com> * tree-vect-stmts.c (vectorizable_comparison): Add diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 71fc514..5d35261 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -285,7 +285,7 @@ "" "@ ccmp\\t%<w>2, %<w>3, %k5, %m4 - ccmp\\t%<w>2, %<w>3, %k5, %m4 + ccmp\\t%<w>2, %3, %k5, %m4 ccmn\\t%<w>2, #%n3, %k5, %m4" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1733,7 +1733,7 @@ "" "@ adds\\t%<w>0, %<w>1, %<w>2 - adds\\t%<w>0, %<w>1, %<w>2 + adds\\t%<w>0, %<w>1, %2 subs\\t%<w>0, %<w>1, #%n2" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1750,7 +1750,7 @@ "" "@ adds\\t%w0, %w1, %w2 - adds\\t%w0, %w1, %w2 + adds\\t%w0, %w1, %2 subs\\t%w0, %w1, #%n2" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -1932,7 +1932,7 @@ "" "@ cmn\\t%<w>0, %<w>1 - cmn\\t%<w>0, %<w>1 + cmn\\t%<w>0, %1 cmp\\t%<w>0, #%n1" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -2878,7 +2878,7 @@ "" "@ cmp\\t%<w>0, %<w>1 - cmp\\t%<w>0, %<w>1 + cmp\\t%<w>0, %1 cmn\\t%<w>0, #%n1" [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) @@ -3312,7 +3312,7 @@ "" "@ <logical>\\t%<w>0, %<w>1, %<w>2 - <logical>\\t%<w>0, %<w>1, %<w>2 + <logical>\\t%<w>0, %<w>1, %2 <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" [(set_attr "type" "logic_reg,logic_imm,neon_logic") (set_attr "simd" "*,*,yes")] |