diff options
| author | James Van Artsdalen <jrv@gnu.org> | 1992-11-12 13:37:42 +0000 |
|---|---|---|
| committer | James Van Artsdalen <jrv@gnu.org> | 1992-11-12 13:37:42 +0000 |
| commit | e1f998ad669d4b1244255742eab338eaf06508d5 (patch) | |
| tree | 5c9b59753d0fd01a8df615f782bae81e2647e89b | |
| parent | 8f2400848464baf07d6b970cef03d864102982a0 (diff) | |
| download | gcc-e1f998ad669d4b1244255742eab338eaf06508d5.zip gcc-e1f998ad669d4b1244255742eab338eaf06508d5.tar.gz gcc-e1f998ad669d4b1244255742eab338eaf06508d5.tar.bz2 | |
(floatMN2 recognizers): Don't omit mode on a match_operand that might be reloaded.
(floatMN2 recognizers): Don't omit mode on a match_operand that might
be reloaded. Split into separate patterns for each mode.
(zero_extract test): Disable for now.
From-SVN: r2747
| -rw-r--r-- | gcc/config/i386/i386.md | 55 |
1 files changed, 42 insertions, 13 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index bc22370..dca7bb6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1305,11 +1305,9 @@ ;; This will convert from SImode or DImode to MODE_FLOAT. (define_insn "" - [(set (match_operand 0 "register_operand" "=f,f") - (match_operator 2 "float_op" - [(match_operand:DI 1 "general_operand" "m,!*r")]))] - "TARGET_80387 && GET_MODE (operands[0]) == GET_MODE (operands[2]) - && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (float:DF (match_operand:DI 1 "general_operand" "m,!*r")))] + "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) @@ -1324,11 +1322,43 @@ }") (define_insn "" - [(set (match_operand 0 "register_operand" "=f,f") - (match_operator 2 "float_op" - [(match_operand:SI 1 "general_operand" "m,!*r")]))] - "TARGET_80387 && GET_MODE (operands[0]) == GET_MODE (operands[2]) - && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (float:SF (match_operand:DI 1 "general_operand" "m,!*r")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (float:DF (match_operand:SI 1 "general_operand" "m,!*r")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (float:SF (match_operand:SI 1 "general_operand" "m,!*r")))] + "TARGET_80387" "* { if (NON_STACK_REG_P (operands[1])) @@ -2939,6 +2969,7 @@ ;; ??? All bets are off if operand 0 is a volatile MEM reference. +/* (define_insn "" [(set (cc0) (zero_extract (match_operand 0 "general_operand" "rm") (match_operand:SI 1 "const_int_operand" "n") @@ -2955,8 +2986,6 @@ if (! REG_P (operands[0]) || QI_REG_P (operands[0])) { - /* We may set the sign bit spuriously. */ - if ((mask & ~0xff) == 0) { cc_status.flags |= CC_NOT_NEGATIVE; @@ -2999,7 +3028,7 @@ return AS2 (test%L1,%0,%1); }") - +*/ (define_insn "" [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") (const_int 1) |