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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2014-02-25 10:20:40 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2014-02-25 10:20:40 +0000 |
| commit | db57bbc9b26143a2efb24868ce1a0cb8ed653447 (patch) | |
| tree | ce9c0e97460f7c8e2f8900b4796a62a7cf1715b8 | |
| parent | 43b3f52f4a5c6c6f03039a06da6006e1b5c44f14 (diff) | |
| download | gcc-db57bbc9b26143a2efb24868ce1a0cb8ed653447.zip gcc-db57bbc9b26143a2efb24868ce1a0cb8ed653447.tar.gz gcc-db57bbc9b26143a2efb24868ce1a0cb8ed653447.tar.bz2 | |
re PR target/55426 (gcc.target/arm/neon-vld1_dupQ.c ICEs on armeb)
PR target/55426
* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
conversions.
From-SVN: r208116
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 14 |
2 files changed, 15 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0f3d80c..4042cf9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/55426 + * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit + conversions. + 2014-02-25 Ilya Tocar <ilya.tocar@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET), diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index d9d3547..7ca47a7 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1257,11 +1257,15 @@ enum reg_class VFPv2. In big-endian mode, modes greater than word size (i.e. DFmode) are stored in VFP registers in little-endian order. We can't describe that accurately to - GCC, so avoid taking subregs of such values. */ -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (TARGET_VFP && TARGET_BIG_END \ - && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ - || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ + GCC, so avoid taking subregs of such values. + The only exception is going from a 128-bit to a 64-bit type. In that case + the data layout happens to be consistent for big-endian, so we explicitly allow + that case. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (TARGET_VFP && TARGET_BIG_END \ + && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ + && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ + || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ && reg_classes_intersect_p (VFP_REGS, (CLASS))) /* The class value for index registers, and the one for base regs. */ |