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author | Michael Meissner <meissner@gcc.gnu.org> | 1993-03-17 22:22:35 +0000 |
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committer | Michael Meissner <meissner@gcc.gnu.org> | 1993-03-17 22:22:35 +0000 |
commit | d1399bd0ff3893bb9ebea7b977c7f3ec91b728b0 (patch) | |
tree | 8ad954bb749bf726c6eb08ad4defbd6590900880 | |
parent | 16594451917dbcd49cd3031fd7cf65f10f6a8224 (diff) | |
download | gcc-d1399bd0ff3893bb9ebea7b977c7f3ec91b728b0.zip gcc-d1399bd0ff3893bb9ebea7b977c7f3ec91b728b0.tar.gz gcc-d1399bd0ff3893bb9ebea7b977c7f3ec91b728b0.tar.bz2 |
Add -mlong-calls.
From-SVN: r3770
-rw-r--r-- | gcc/config/mips/mips.h | 36 | ||||
-rw-r--r-- | gcc/config/mips/mips.md | 42 |
2 files changed, 46 insertions, 32 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 9cceff2..f3ca4f0 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -463,7 +463,7 @@ while (0) /* Print subsidiary information on the compiler version in use. */ -#define MIPS_VERSION "[AL 1.1, MM 34]" +#define MIPS_VERSION "[AL 1.1, MM 35]" #ifndef MACHINE_TYPE #define MACHINE_TYPE "BSD Mips" @@ -683,23 +683,18 @@ do { \ #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */ #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/ -#define MASK_UNUSED1 0x00001000 -#define MASK_UNUSED2 0x00002000 -#define MASK_UNUSED3 0x00004000 -#define MASK_UNUSED4 0x00008000 -#define MASK_UNUSED5 0x00010000 -#define MASK_UNUSED6 0x00020000 -#define MASK_UNUSED7 0x00040000 -#define MASK_UNUSED8 0x00080000 +#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */ +#define MASK_UNUSED1 0x00002000 +#define MASK_UNUSED2 0x00004000 +#define MASK_UNUSED3 0x00008000 +#define MASK_UNUSED4 0x00010000 +#define MASK_UNUSED5 0x00020000 +#define MASK_UNUSED6 0x00040000 +#define MASK_UNUSED7 0x00080000 /* Dummy switches used only in spec's*/ #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */ - /* switches not used yet */ -#define MASK_WC8 0x00000000 /* wchar's are 8 bits, not 32 */ -#define MASK_WC16 0x00000000 /* wchar's are 16 bits, not 32 */ -#define MASK_WC32 0x00000000 /* dummy for consistency */ - /* Debug switches, not documented */ #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */ #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */ @@ -755,15 +750,13 @@ do { \ /* OSF pic references to externs */ #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) - /* wchar size */ -#define TARGET_WC8 (target_flags & MASK_WC8) -#define TARGET_WC16 (target_flags & MASK_WC16) -#define TARGET_WC32 ((target_flags & (MASK_WC8 | MASK_WC16)) == 0) - /* software floating point */ #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) + /* always call through a register */ +#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) + /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } @@ -787,9 +780,6 @@ do { \ {"no-stats", -MASK_STATS}, \ {"memcpy", MASK_MEMCPY}, \ {"no-memcpy", -MASK_MEMCPY}, \ - {"wc8", MASK_WC8}, \ - {"wc16", MASK_WC16}, \ - {"wc32", MASK_WC32}, \ {"mips-tfile", MASK_MIPS_TFILE}, \ {"no-mips-tfile", -MASK_MIPS_TFILE}, \ {"soft-float", MASK_SOFT_FLOAT}, \ @@ -800,6 +790,8 @@ do { \ {"no-abicalls", -MASK_ABICALLS}, \ {"half-pic", MASK_HALF_PIC}, \ {"no-half-pic", -MASK_HALF_PIC}, \ + {"long-calls", MASK_LONG_CALLS}, \ + {"no-long-calls", -MASK_LONG_CALLS}, \ {"debug", MASK_DEBUG}, \ {"debuga", MASK_DEBUG_A}, \ {"debugb", MASK_DEBUG_B}, \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 41b044c..57ae3cb 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4054,7 +4054,7 @@ move\\t%0,%z4\\n\\ if (operands[0]) /* eliminate unused code warnings */ { addr = XEXP (operands[0], 0); - if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr)) + if (GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) XEXP (operands[0], 0) = force_reg (FUNCTION_MODE, addr); /* In order to pass small structures by value in registers @@ -4074,17 +4074,17 @@ move\\t%0,%z4\\n\\ emit_insn (RTVEC_ELT (adjust, i)); } - emit_call_insn (gen_call_internal (operands[0], operands[1], - gen_rtx (REG, Pmode, GP_REG_FIRST + 31))); + emit_call_insn (gen_call_internal1 (operands[0], operands[1], + gen_rtx (REG, Pmode, GP_REG_FIRST + 31))); DONE; } }") -(define_insn "call_internal" +(define_insn "call_internal1" [(call (match_operand 0 "memory_operand" "m") (match_operand 1 "" "i")) (clobber (match_operand:SI 2 "register_operand" "=d"))] - "" + "!TARGET_LONG_CALLS" "* { register rtx target = XEXP (operands[0], 0); @@ -4108,6 +4108,17 @@ move\\t%0,%z4\\n\\ (set_attr "mode" "none") (set_attr "length" "1")]) +(define_insn "call_internal2" + [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "TARGET_LONG_CALLS" + "%*jal\\t%2,%0" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + + ;; calls.c now passes a fourth argument, make saber happy (define_expand "call_value" @@ -4124,7 +4135,7 @@ move\\t%0,%z4\\n\\ if (operands[0]) /* eliminate unused code warning */ { addr = XEXP (operands[1], 0); - if (GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr)) + if (GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) XEXP (operands[1], 0) = force_reg (FUNCTION_MODE, addr); /* In order to pass small structures by value in registers @@ -4144,20 +4155,20 @@ move\\t%0,%z4\\n\\ emit_insn (RTVEC_ELT (adjust, i)); } - emit_call_insn (gen_call_value_internal (operands[0], operands[1], operands[2], - gen_rtx (REG, Pmode, GP_REG_FIRST + 31))); + emit_call_insn (gen_call_value_internal1 (operands[0], operands[1], operands[2], + gen_rtx (REG, Pmode, GP_REG_FIRST + 31))); DONE; } }") -(define_insn "call_value_internal" +(define_insn "call_value_internal1" [(set (match_operand 0 "register_operand" "=df") (call (match_operand 1 "memory_operand" "m") (match_operand 2 "" "i"))) (clobber (match_operand:SI 3 "register_operand" "=d"))] - "" + "!TARGET_LONG_CALLS" "* { register rtx target = XEXP (operands[1], 0); @@ -4181,6 +4192,17 @@ move\\t%0,%z4\\n\\ (set_attr "mode" "none") (set_attr "length" "1")]) +(define_insn "call_value_internal2" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "TARGET_LONG_CALLS" + "%*jal\\t%3,%1" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + ;; ;; .................... |