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| author | Vladimir Makarov <vmakarov@tofu.to.cygnus.com> | 1999-05-07 16:20:37 +0000 |
|---|---|---|
| committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 1999-05-07 16:20:37 +0000 |
| commit | d0ae1ce326d07f8217610a3a4e5baf456318aa1a (patch) | |
| tree | f86d6d17b5bbd435115ad4bd1659c890d2bc1450 | |
| parent | 52ecdfda6590bc24e48db6bbe0cf210d39c26572 (diff) | |
| download | gcc-d0ae1ce326d07f8217610a3a4e5baf456318aa1a.zip gcc-d0ae1ce326d07f8217610a3a4e5baf456318aa1a.tar.gz gcc-d0ae1ce326d07f8217610a3a4e5baf456318aa1a.tar.bz2 | |
sparc.h (GO_IF_LEGITIMATE_ADDRESS): Prohibit REG+REG addressing for TFmode when there are no instructions which...
Fri May 7 19:10:15 1999 Vladimir Makarov <vmakarov@tofu.to.cygnus.com>
* sparc.h (GO_IF_LEGITIMATE_ADDRESS): Prohibit REG+REG addressing
for TFmode when there are no instructions which accept REG+REG
instructions.
From-SVN: r26825
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.h | 17 |
2 files changed, 23 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d33a850..e264420 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Fri May 7 19:10:15 1999 Vladimir Makarov <vmakarov@tofu.to.cygnus.com> + + * sparc.h (GO_IF_LEGITIMATE_ADDRESS): Prohibit REG+REG addressing + for TFmode when there are no instructions which accept REG+REG + instructions. + Fri May 7 12:38:54 1999 Jim Wilson <wilson@cygnus.com> * mips/elf64.h (MAKE_DECL_ONE_ONLY, UNIQUE_SECTION_P): Define. diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index a220ce7..b10d096 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -2489,12 +2489,29 @@ extern struct rtx_def *sparc_builtin_saveregs (); else if (RTX_OK_FOR_BASE_P (op0)) \ { \ if (RTX_OK_FOR_INDEX_P (op1) \ + /* We prohibit REG + REG for TFmode when \ + there are no instructions which accept \ + REG+REG instructions. We do this \ + because REG+REG is not an offsetable \ + address. If we get the situation \ + in reload where source and destination \ + of a movtf pattern are both MEMs with \ + REG+REG address, then only one of them \ + gets converted to an offsetable \ + address. */ \ + && (MODE != TFmode \ + || (TARGET_FPU && TARGET_ARCH64 \ + && TARGET_V9 && TARGET_HARD_QUAD))\ || RTX_OK_FOR_OFFSET_P (op1)) \ goto ADDR; \ } \ else if (RTX_OK_FOR_BASE_P (op1)) \ { \ if (RTX_OK_FOR_INDEX_P (op0) \ + /* See the previous comment. */ \ + && (MODE != TFmode \ + || (TARGET_FPU && TARGET_ARCH64 \ + && TARGET_V9 && TARGET_HARD_QUAD))\ || RTX_OK_FOR_OFFSET_P (op0)) \ goto ADDR; \ } \ |