[ARM] Fix PR target/64460: Set 'shift' attr properly on some patterns.

	PR target/64460
	* config/arm/arm.md (*<arith_shift_insn>_multsi): Set 'shift' to 2.
	(*<arith_shift_insn>_shiftsi): Set 'shift' attr to 3.

	* gcc.target/arm/pr64460_1.c: New test.

From-SVN: r219583

4 files changed, 82 insertions, 2 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2f19b49..611f0a7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-01-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/64460
+	* config/arm/arm.md (*<arith_shift_insn>_multsi): Set 'shift' to 2.
+	(*<arith_shift_insn>_shiftsi): Set 'shift' attr to 3.
+
 2015-01-14  Matthew Fortune  <matthew.fortune@imgtec.com>
 
     	* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Only infer an ISA
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index c61057f..bbefb93 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8262,7 +8262,7 @@
   "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "shift" "4")
+   (set_attr "shift" "2")
    (set_attr "arch" "a,t2")
    (set_attr "type" "alu_shift_imm")])
 
@@ -8277,7 +8277,7 @@
   "<arith_shift_insn>%?\\t%0, %1, %3%S2"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "shift" "4")
+   (set_attr "shift" "3")
    (set_attr "arch" "a,t2,a")
    (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 00dc23f..071c47d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-01-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/64460
+	* gcc.target/arm/pr64460_1.c: New test.
+
 2015-01-14  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/64493
diff --git a/gcc/testsuite/gcc.target/arm/pr64460_1.c b/gcc/testsuite/gcc.target/arm/pr64460_1.c
new file mode 100644
index 0000000..ee6ad4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr64460_1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=xscale" } */
+
+typedef unsigned int size_t;
+typedef short unsigned int __uint16_t;
+typedef long unsigned int __uint32_t;
+typedef unsigned int __uintptr_t;
+typedef __uint16_t uint16_t ;
+typedef __uint32_t uint32_t ;
+typedef __uintptr_t uintptr_t;
+typedef uint32_t Objects_Id;
+typedef uint16_t Objects_Maximum;
+typedef struct { } Objects_Control;
+
+static __inline__ void *_Addresses_Align_up (void *address, size_t alignment)
+{
+	uintptr_t mask = alignment - (uintptr_t)1;
+	return (void*)(((uintptr_t)address + mask) & ~mask);
+}
+
+typedef struct {
+	Objects_Id minimum_id;
+	Objects_Maximum maximum;
+	_Bool
+		auto_extend;
+	Objects_Maximum allocation_size;
+	void **object_blocks;
+} Objects_Information;
+
+extern uint32_t _Objects_Get_index (Objects_Id);
+extern void** _Workspace_Allocate (size_t);
+
+void _Objects_Extend_information (Objects_Information *information)
+{
+	uint32_t block_count;
+	uint32_t minimum_index;
+	uint32_t maximum;
+	size_t block_size;
+	_Bool
+		do_extend =
+		minimum_index = _Objects_Get_index( information->minimum_id );
+	if ( information->object_blocks ==
+			((void *)0)
+	   )
+		block_count = 0;
+	else {
+		block_count = information->maximum / information->allocation_size;
+	}
+	if ( do_extend ) {
+		void **object_blocks;
+		uintptr_t object_blocks_size;
+		uintptr_t inactive_per_block_size;
+		object_blocks_size = (uintptr_t)_Addresses_Align_up(
+				(void*)(block_count * sizeof(void*)),
+				8
+				);
+		inactive_per_block_size =
+			(uintptr_t)_Addresses_Align_up(
+					(void*)(block_count * sizeof(uint32_t)),
+					8
+					);
+		block_size = object_blocks_size + inactive_per_block_size +
+			((maximum + minimum_index) * sizeof(Objects_Control *));
+		if ( information->auto_extend ) {
+			object_blocks = _Workspace_Allocate( block_size );
+		} else {
+		}
+	}
+}