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| author | Richard Kenner <kenner@gcc.gnu.org> | 1994-05-06 12:52:00 -0400 |
|---|---|---|
| committer | Richard Kenner <kenner@gcc.gnu.org> | 1994-05-06 12:52:00 -0400 |
| commit | c9325fd6c62f615e1be9a4d009f23cb770d90c68 (patch) | |
| tree | ecaf70bad460485ebf09ec34d6cd6327855afa32 | |
| parent | 8b7b2e363992f3001ad15114e3305600e14170c4 (diff) | |
| download | gcc-c9325fd6c62f615e1be9a4d009f23cb770d90c68.zip gcc-c9325fd6c62f615e1be9a4d009f23cb770d90c68.tar.gz gcc-c9325fd6c62f615e1be9a4d009f23cb770d90c68.tar.bz2 | |
(addsi3, subsi3): Add define_expand to make adddi3/subdi3; old pattern
is now anonymous.
From-SVN: r7226
| -rw-r--r-- | gcc/config/alpha/alpha.md | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index f42cda6..c7ca0f0 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -85,7 +85,23 @@ cvtql %1,%0\;cvtlq %0,%0" [(set_attr "type" "iaddlog,ld,fpop")]) -(define_insn "addsi3" +;; Do addsi3 the way expand_binop would do if we didn't have one. This +;; generates better code. We have the anonymous addsi3 pattern below in +;; case combine wants to make it. +(define_expand "addsi3" + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") + (match_operand:SI 2 "add_operand" "")))] + "" + " +{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), + gen_rtx (PLUS, DImode, + gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2])))); + DONE; +} ") + +(define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") (match_operand:SI 2 "add_operand" "rI,O,K,L")))] @@ -273,7 +289,21 @@ "subq $31,%1,%0" [(set_attr "type" "iaddlog")]) -(define_insn "subsi3" +(define_expand "subsi3" + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") + (match_operand:SI 2 "reg_or_8bit_operand" "")))] + "" + " +{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), + gen_rtx (MINUS, DImode, + gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2])))); + DONE; + +} ") + +(define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] |