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| author | Bill Schmidt <wschmidt@linux.ibm.com> | 2022-01-21 13:13:11 -0600 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.ibm.com> | 2022-01-21 13:14:19 -0600 |
| commit | afe91e2566f47a6041f45095a48fc255625cb468 (patch) | |
| tree | 3f08cd1e443cb63bfa672a83262cf7f556bb7e8b | |
| parent | 518aad6a161598fd49dffaa5b5c8da477fda160a (diff) | |
| download | gcc-afe91e2566f47a6041f45095a48fc255625cb468.zip gcc-afe91e2566f47a6041f45095a48fc255625cb468.tar.gz gcc-afe91e2566f47a6041f45095a48fc255625cb468.tar.bz2 | |
rs6000: Support vector float/double for vec_sldw
2022-01-21 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-overload.def (VEC_SLDW): Add instances for
vector float and vector double.
gcc/testsuite/
* gcc.target/powerpc/builtins-4.c: Add two test variants. Adjust
assembler counts.
| -rw-r--r-- | gcc/config/rs6000/rs6000-overload.def | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/builtins-4.c | 34 |
2 files changed, 28 insertions, 10 deletions
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index e279153..7d030ab 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -3401,6 +3401,10 @@ XXSLDWI_2DI XXSLDWI_VSLL vull __builtin_vec_sldw (vull, vull, const int); XXSLDWI_2DI XXSLDWI_VULL + vf __builtin_vec_sldw (vf, vf, const int); + XXSLDWI_4SF XXSLDWI_VF + vd __builtin_vec_sldw (vd, vd, const int); + XXSLDWI_2DF XXSLDWI_VD [VEC_SLL, vec_sll, __builtin_vec_sll] vsc __builtin_vec_sll (vsc, vuc); diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4.c b/gcc/testsuite/gcc.target/powerpc/builtins-4.c index 4e3b543..f65e582 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-4.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-4.c @@ -119,6 +119,18 @@ test_vul_sldw_vul_vul (vector unsigned long long x, return vec_sldw (x, y, 3); } +vector float +test_vf_sldw_vf_vf (vector float x, vector float y) +{ + return vec_sldw (x, y, 3); +} + +vector double +test_vd_sldw_vd_vd (vector double x, vector double y) +{ + return vec_sldw (x, y, 1); +} + vector signed int long long test_sll_vsill_vsill_vuc (vector signed long long int x, vector unsigned char y) @@ -146,14 +158,16 @@ test_sll_vuill_vuill_vuc (vector unsigned long long int x, test_slo_vsll_slo_vsll_vuc 1 vslo test_slo_vull_slo_vull_vsc 1 vslo test_slo_vull_slo_vull_vuc 1 vslo - test_vsc_sldw_vsc_vsc 1 xxlor - test_vuc_sldw_vuc_vuc 1 xxlor - test_vssi_sldw_vssi_vssi 1 xxlor - test_vusi_sldw_vusi_vusi 1 xxlor - test_vsi_sldw_vsi_vsi 1 xxlor - test_vui_sldw_vui_vui 1 xxlor - test_vsl_sldw_vsl_vsl 1 xxlor - test_vul_sldw_vul_vul 1 xxlor + test_vsc_sldw_vsc_vsc 1 xxlor, 1 xxsldwi + test_vuc_sldw_vuc_vuc 1 xxlor, 1 xxsldwi + test_vssi_sldw_vssi_vssi 1 xxlor, 1 xxsldwi + test_vusi_sldw_vusi_vusi 1 xxlor, 1 xxsldwi + test_vsi_sldw_vsi_vsi 1 xxlor, 1 xxsldwi + test_vui_sldw_vui_vui 1 xxlor, 1 xxsldwi + test_vsl_sldw_vsl_vsl 1 xxlor, 1 xxsldwi + test_vul_sldw_vul_vul 1 xxlor, 1 xxsldwi + test_vf_sldw_vf_vf 1 xxlor, 1 xxsldwi + test_vd_sldw_vd_vd 1 xxlor, 1 xxsldwi test_sll_vsill_vsill_vuc 1 vsl test_sll_vuill_vuill_vuc 1 vsl */ @@ -161,6 +175,6 @@ test_sll_vuill_vuill_vuc (vector unsigned long long int x, /* { dg-final { scan-assembler-times "xvnabssp" 1 } } */ /* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */ /* { dg-final { scan-assembler-times "vslo" 4 } } */ -/* { dg-final { scan-assembler-times "xxlor" 30 } } */ +/* { dg-final { scan-assembler-times "xxlor" 32 } } */ /* { dg-final { scan-assembler-times {\mvsl\M} 5 } } */ - +/* { dg-final { scan-assembler-times {\mxxsldwi\M} 10 } } */ |