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| author | Kito Cheng <kito.cheng@sifive.com> | 2022-09-05 21:36:45 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-09-05 21:46:01 +0800 |
| commit | ae97ba1efcd66d73d3631addf4c09f55e12d34f5 (patch) | |
| tree | 7370394e1144ae1fb897c5321b1ac2dfcb8f959d | |
| parent | 48b9c7d5d329a75d0ceb4e3b26a11bc3b6370f4c (diff) | |
| download | gcc-ae97ba1efcd66d73d3631addf4c09f55e12d34f5.zip gcc-ae97ba1efcd66d73d3631addf4c09f55e12d34f5.tar.gz gcc-ae97ba1efcd66d73d3631addf4c09f55e12d34f5.tar.bz2 | |
RISC-V: Fix division instructions for `m` with `zmmul` extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Fix wrong
condition for MASK_DIV and simplify incompatible checking.
* config/riscv/riscv.md (muldi3): Adding parentheses.
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 8 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 2 |
2 files changed, 3 insertions, 7 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b5252b4..675d92c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5277,14 +5277,10 @@ riscv_option_override (void) /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) - if(!TARGET_ZMMUL) - target_flags |= MASK_DIV; + target_flags |= MASK_DIV; else if (!TARGET_MUL && TARGET_DIV) error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); - - if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV) - warning (0, "%<-mdiv%> cannot be used when %<ZMMUL%> extension is present"); - + /* Likewise floating-point division and square root. */ if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d2dfde2..014206f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -752,7 +752,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) |