diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-08-07 19:15:58 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-08-07 19:15:58 +0000 |
| commit | 9b6fb97c99abe64147f82a3ea6e6ed598e387482 (patch) | |
| tree | a17e8c78f837d27323e987efa07cd86a13a484aa | |
| parent | 61ee25b9e7d84fbb18218887d1fecfb10f72993a (diff) | |
| download | gcc-9b6fb97c99abe64147f82a3ea6e6ed598e387482.zip gcc-9b6fb97c99abe64147f82a3ea6e6ed598e387482.tar.gz gcc-9b6fb97c99abe64147f82a3ea6e6ed598e387482.tar.bz2 | |
[AArch64] Fix INSR for zero floats
We used INSR to handle zero integers but not zero floats.
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/constraints.md (Z): Handle floating-point zeros too.
* config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/init_13.c: New test.
From-SVN: r274193
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/constraints.md | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/init_13.c | 17 |
5 files changed, 30 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ef6c201..45050ed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/constraints.md (Z): Handle floating-point zeros too. + * config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise. + +2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add MOVPRFX alternatives. Make the GPR alternatives more expensive than the FPR ones. diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 21f9549..824000a 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -114,8 +114,8 @@ (match_test "aarch64_float_const_zero_rtx_p (op)"))) (define_constraint "Z" - "Integer constant zero." - (match_test "op == const0_rtx")) + "Integer or floating-point constant zero." + (match_test "op == CONST0_RTX (GET_MODE (op))")) (define_constraint "Ush" "A constraint that matches an absolute symbolic address high part." diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 10100ca..2cd0b87 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -57,9 +57,9 @@ (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) (define_predicate "aarch64_reg_or_zero" - (and (match_code "reg,subreg,const_int") + (and (match_code "reg,subreg,const_int,const_double") (ior (match_operand 0 "register_operand") - (match_test "op == const0_rtx")))) + (match_test "op == CONST0_RTX (GET_MODE (op))")))) (define_predicate "aarch64_reg_or_fp_zero" (ior (match_operand 0 "register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 22cf0e9..cf4cbab 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * gcc.target/aarch64/sve/init_13.c: New test. + +2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into a temporary FPR. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_13.c b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c new file mode 100644 index 0000000..eea4170 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c @@ -0,0 +1,17 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef float vnx4sf __attribute__((vector_size (32))); + +/* +** foo: +** mov (z[0-9]+\.s), s0 +** insr \1, wzr +** ... +*/ +vnx4sf +foo (float a) +{ + return (vnx4sf) { 0.0f, a, a, a, a, a, a, a }; +} |