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| author | Aaron Sawdey <acsawdey@linux.vnet.ibm.com> | 2017-03-22 17:47:55 +0000 |
|---|---|---|
| committer | Aaron Sawdey <acsawdey@gcc.gnu.org> | 2017-03-22 12:47:55 -0500 |
| commit | 992113522d88d5676b29a74bde4f3d5f21fd0c85 (patch) | |
| tree | 0d8a161baa97b5718c8ba78d3307c5f8182be606 | |
| parent | 2f029c0898b6c1afcfe31c9f459f1ff43e9cce3f (diff) | |
| download | gcc-992113522d88d5676b29a74bde4f3d5f21fd0c85.zip gcc-992113522d88d5676b29a74bde4f3d5f21fd0c85.tar.gz gcc-992113522d88d5676b29a74bde4f3d5f21fd0c85.tar.bz2 | |
re PR target/80123 (libgomp tests pr66199-2.c and pr66199-5.c fail with -mcpu=power9)
2017-03-21 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
PR target/80123
* doc/md.texi (Constraints): Document wA constraint.
* config/rs6000/constraints.md (wA): New.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
(rs6000_init_hard_regno_mode_ok): Init wA constraint.
* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.
From-SVN: r246394
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/constraints.md | 3 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 1 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 2 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 3 |
6 files changed, 24 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7202cf..eaf7650 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-03-21 Aaron Sawdey <acsawdey@linux.vnet.ibm.com> + + PR target/80123 + * doc/md.texi (Constraints): Document wA constraint. + * config/rs6000/constraints.md (wA): New. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class. + (rs6000_init_hard_regno_mode_ok): Init wA constraint. + * config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New. + * config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint. + 2017-03-22 Cesar Philippidis <cesar@codesourcery.com> PR c++/80029 diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 3165124..44f45d8 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -133,6 +133,9 @@ (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") +(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" + "BASE_REGS if 64-bit instructions are enabled or NO_REGS.") + ;; wB needs ISA 2.07 VUPKHSW (define_constraint "wB" "Signed 5-bit constant integer that can be loaded into an altivec register." diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f8600b8..9db85e6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2468,6 +2468,7 @@ rs6000_debug_reg_global (void) "wx reg_class = %s\n" "wy reg_class = %s\n" "wz reg_class = %s\n" + "wA reg_class = %s\n" "wH reg_class = %s\n" "wI reg_class = %s\n" "wJ reg_class = %s\n" @@ -2500,6 +2501,7 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]], @@ -3210,7 +3212,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } if (TARGET_POWERPC64) - rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; + { + rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS; + } if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */ { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index da6fd52..3780a49 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1612,6 +1612,7 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ RS6000_CONSTRAINT_wy, /* VSX register for SF */ RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ + RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f4f1663..bfc1527 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3072,7 +3072,7 @@ "=<VSa>, <VSa>,we,<VS_64dm>") (vec_duplicate:VSX_D (match_operand:<VS_scalar> 1 "splat_input_operand" - "<VS_64reg>,Z, b, wr")))] + "<VS_64reg>,Z, b, wA")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ xxpermdi %x0,%x1,%x1,0 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index c9d937d..dde3644 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3122,6 +3122,9 @@ FP or VSX register to perform ISA 2.07 float ops or NO_REGS. @item wz Floating point register if the LFIWZX instruction is enabled or NO_REGS. +@item wA +Address base register if 64-bit instructions are enabled or NO_REGS. + @item wB Signed 5-bit constant integer that can be loaded into an altivec register. |