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authorKazu Hirata <kazu@cs.umass.edu>2004-09-19 04:02:34 +0000
committerKazu Hirata <kazu@gcc.gnu.org>2004-09-19 04:02:34 +0000
commit938688cdf7a89bd099110a8b4751757a2242b835 (patch)
tree4b550ec8b1a12738e3ceda463e5baeb64d4e3285
parentfdabe5c2ef530b511e8b86fb814c8f226ec693d9 (diff)
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cris.h: Preserve the original spelling in a quote.
* config/cris/cris.h: Preserve the original spelling in a quote. From-SVN: r87720
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/cris/cris.h2
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f06c542..44cce19 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-09-18 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/cris/cris.h: Preserve the original spelling in a
+ quote.
+
2004-09-18 Jeff Law <law@redhat.com>
* tree-ssa-dom.c (nonzero_vars_stack, vrp_variables_stack): New
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 14c6a95..d7da183 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -336,7 +336,7 @@ extern int target_flags;
/* Whether or not to work around multiplication instruction hardware bug
when generating code for models where it may be present. From the
trouble report for Etrax 100 LX: "A multiply operation may cause
- incorrect cache behavior under some specific circumstances. The
+ incorrect cache behaviour under some specific circumstances. The
problem can occur if the instruction following the multiply instruction
causes a cache miss, and multiply operand 1 (source operand) bits
[31:27] matches the logical mapping of the mode register address