re PR target/46280 (Several testcases FAIL with 16byte alignment ABI warning on Solaris 8/9 x86)

	gcc:
	* config/i386/i386.c (ix86_function_arg_boundary): Fix warning
	message.

	gcc/testsuite:
	* gcc.dg/pr35442.c: Adapt warning.

	PR target/46280
	* g++.dg/eh/simd-2.C: Add -msse to dg-options, add
	dg-require-effective-target sse_runtime for for i?86-*-*, x86_64-*-*.
	* g++.dg/torture/pr36444.C: Add dg-options -msse for
	i?86-*-* x86_64-*-*.
	* g++.dg/torture/pr36445.C: Likewise.
	* gcc.c-torture/compile/pr34856.c: Likewise.
	* gcc.c-torture/compile/pr39928-1.c: Likewise.
	* gcc.c-torture/compile/vector-1.c: Likewise.
	* gcc.c-torture/compile/vector-2.c: Likewise.
	* gcc.dg/pr32912-1.c: Likewise.
	* gcc.c-torture/execute/va-arg-25.c: Move ...
	* gcc.dg/torture/va-arg-25.c: ... here.
	Add dg-do run.
	Add dg-options -msse, dg-require-effective-target sse_runtime for
	for i?86-*-*, x86_64-*-*.
	* gcc.c-torture/execute/vector-1.c: Likewise.
	* gcc.c-torture/execute/vector-2.c: Likewise.
	* gcc.dg/tree-ssa/forwprop-5.c: Add -msse to dg-options for
	i?86-*-*, x86_64-*-*.
	* gcc.dg/tree-ssa/fre-vce-1.c: Likewise.
	* gcc.dg/tree-ssa/sra-4.c: Likewise.
	* gcc.dg/tree-ssa/vector-1.c: Likewise.
	* gcc.dg/tree-ssa/vector-2.c: Likewise.
	* gcc.target/i386/vect-args.c: Add -Wno-psabi to dg-options.

From-SVN: r166444

21 files changed, 66 insertions, 5 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 408a054..ae81d67 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2010-11-08  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* config/i386/i386.c (ix86_function_arg_boundary): Fix warning
+	message.
 
 2010-11-08  Basile Starynkevitch  <basile@starynkevitch.net>
 
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index b4ba2c1..9efc0df 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -7147,7 +7147,7 @@ ix86_function_arg_boundary (enum machine_mode mode, const_tree type)
 	{
 	  warned = true;
 	  inform (input_location,
-		  "The ABI of passing parameter with %dbyte"
+		  "The ABI for passing parameters with %d-byte"
 		  " alignment has changed in GCC 4.6",
 		  align / BITS_PER_UNIT);
 	}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 600f768..74d974b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,33 @@
+2010-11-08  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* gcc.dg/pr35442.c: Adapt warning.
+
+	PR target/46280
+	* g++.dg/eh/simd-2.C: Add -msse to dg-options, add
+	dg-require-effective-target sse_runtime for for i?86-*-*, x86_64-*-*.
+	* g++.dg/torture/pr36444.C: Add dg-options -msse for
+	i?86-*-* x86_64-*-*.
+	* g++.dg/torture/pr36445.C: Likewise.
+	* gcc.c-torture/compile/pr34856.c: Likewise.
+	* gcc.c-torture/compile/pr39928-1.c: Likewise.
+	* gcc.c-torture/compile/vector-1.c: Likewise.
+	* gcc.c-torture/compile/vector-2.c: Likewise.
+	* gcc.dg/pr32912-1.c: Likewise.
+	* gcc.c-torture/execute/va-arg-25.c: Move ...
+	* gcc.dg/torture/va-arg-25.c: ... here.
+	Add dg-do run.
+	Add dg-options -msse, dg-require-effective-target sse_runtime for
+	for i?86-*-*, x86_64-*-*.
+	* gcc.c-torture/execute/vector-1.c: Likewise.
+	* gcc.c-torture/execute/vector-2.c: Likewise.
+	* gcc.dg/tree-ssa/forwprop-5.c: Add -msse to dg-options for
+	i?86-*-*, x86_64-*-*.
+	* gcc.dg/tree-ssa/fre-vce-1.c: Likewise.
+	* gcc.dg/tree-ssa/sra-4.c: Likewise.
+	* gcc.dg/tree-ssa/vector-1.c: Likewise.
+	* gcc.dg/tree-ssa/vector-2.c: Likewise.
+	* gcc.target/i386/vect-args.c: Add -Wno-psabi to dg-options.
+
 2010-11-08  Steve Ellcey  <sje@cup.hp.com>
 
 	* gcc.dg/torture/pr45982.c: Add -std=c99
diff --git a/gcc/testsuite/g++.dg/eh/simd-2.C b/gcc/testsuite/g++.dg/eh/simd-2.C
index da7ef49..2761061 100644
--- a/gcc/testsuite/g++.dg/eh/simd-2.C
+++ b/gcc/testsuite/g++.dg/eh/simd-2.C
@@ -1,10 +1,11 @@
 // Test EH when V4SI SIMD registers are involved.
 // Contributed by Aldy Hernandez (aldy@quesejoda.com).
 // { dg-options "-O -Wno-abi" }
-// { dg-options "-O -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
+// { dg-options "-O -w -msse" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
 // { dg-options "-O -w" { target powerpc*-*-* } }
 // { dg-options "-O -w -maltivec" { target { powerpc*-*-* && vmx_hw } } }
 // { dg-do run }
+// { dg-require-effective-target sse_runtime { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
 
 #include "check-vect.h"
 
diff --git a/gcc/testsuite/g++.dg/torture/pr36444.C b/gcc/testsuite/g++.dg/torture/pr36444.C
index fd20bde..ae639e2 100644
--- a/gcc/testsuite/g++.dg/torture/pr36444.C
+++ b/gcc/testsuite/g++.dg/torture/pr36444.C
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 #define vector __attribute__((vector_size(16) ))
 struct struct1  {
   union {}    vmx;
diff --git a/gcc/testsuite/g++.dg/torture/pr36445.C b/gcc/testsuite/g++.dg/torture/pr36445.C
index 39a7a55..56642e9 100644
--- a/gcc/testsuite/g++.dg/torture/pr36445.C
+++ b/gcc/testsuite/g++.dg/torture/pr36445.C
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 // This used to fail as we would try to expand a VCE where one side had
 // a mode of BLKmode and the other side was a vector mode.
 #define vector __attribute__((vector_size(16) ))
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr34856.c b/gcc/testsuite/gcc.c-torture/compile/pr34856.c
index a2f4369..7b0d596 100644
--- a/gcc/testsuite/gcc.c-torture/compile/pr34856.c
+++ b/gcc/testsuite/gcc.c-torture/compile/pr34856.c
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 #undef __vector
 #define __vector __attribute__((vector_size(16) ))
 typedef __vector signed char qword;
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c b/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c
index 3bee438..1abb5cc 100644
--- a/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c
+++ b/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
 extern __m128 _mm_sub_ps (__m128 __A, __m128 __B);
 extern __m128 _mm_mul_ps (__m128 __A, __m128 __B);
diff --git a/gcc/testsuite/gcc.c-torture/compile/vector-1.c b/gcc/testsuite/gcc.c-torture/compile/vector-1.c
index d22afd5..9be0be1 100644
--- a/gcc/testsuite/gcc.c-torture/compile/vector-1.c
+++ b/gcc/testsuite/gcc.c-torture/compile/vector-1.c
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 #define vector __attribute__((vector_size(16) ))
 struct ss
 {
diff --git a/gcc/testsuite/gcc.c-torture/compile/vector-2.c b/gcc/testsuite/gcc.c-torture/compile/vector-2.c
index 930a9c1..e04d555 100644
--- a/gcc/testsuite/gcc.c-torture/compile/vector-2.c
+++ b/gcc/testsuite/gcc.c-torture/compile/vector-2.c
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
 #define vector __attribute__((vector_size(16) ))
 struct ss
 {
diff --git a/gcc/testsuite/gcc.dg/pr32912-1.c b/gcc/testsuite/gcc.dg/pr32912-1.c
index 1ceb77a..4fcc29a 100644
--- a/gcc/testsuite/gcc.dg/pr32912-1.c
+++ b/gcc/testsuite/gcc.dg/pr32912-1.c
@@ -2,6 +2,8 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -w" } */
 /* { dg-options "-O2 -w -fno-common" { target hppa*-*-hpux* } } */
+/* { dg-options "-O2 -w -msse" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
 
 extern void abort (void);
 
diff --git a/gcc/testsuite/gcc.dg/pr35442.c b/gcc/testsuite/gcc.dg/pr35442.c
index 875cb0b..206853b 100644
--- a/gcc/testsuite/gcc.dg/pr35442.c
+++ b/gcc/testsuite/gcc.dg/pr35442.c
@@ -11,4 +11,4 @@ foo (A a)
 }
 
 /* Ignore a warning that is irrelevant to the purpose of this test.  */
-/* { dg-prune-output "(.*GCC vector passed by reference.*|.*ABI of * passing parameter with.*)" } */
+/* { dg-prune-output "(.*GCC vector passed by reference.*|.*ABI for * passing parameters with.*)" } */
diff --git a/gcc/testsuite/gcc.c-torture/execute/va-arg-25.c b/gcc/testsuite/gcc.dg/torture/va-arg-25.c
index b9f3a1b..8496460 100644
--- a/gcc/testsuite/gcc.c-torture/execute/va-arg-25.c
+++ b/gcc/testsuite/gcc.dg/torture/va-arg-25.c
@@ -1,6 +1,11 @@
 /* Varargs and vectors!  */
 
+/* { dg-do run } */
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
 #include <stdarg.h>
+#include <stdlib.h>
 #include <limits.h>
 
 #define vector __attribute__((vector_size(16)))
diff --git a/gcc/testsuite/gcc.c-torture/execute/vector-1.c b/gcc/testsuite/gcc.dg/torture/vector-1.c
index ff21d68..9ab78aa 100644
--- a/gcc/testsuite/gcc.c-torture/execute/vector-1.c
+++ b/gcc/testsuite/gcc.dg/torture/vector-1.c
@@ -1,5 +1,9 @@
 /* Check that vector extraction works correctly. */
 
+/* { dg-do run } */
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
 #define vector __attribute__((vector_size(16) ))
 
 int f0(vector int t)
diff --git a/gcc/testsuite/gcc.c-torture/execute/vector-2.c b/gcc/testsuite/gcc.dg/torture/vector-2.c
index 55330dd..bff9f82 100644
--- a/gcc/testsuite/gcc.c-torture/execute/vector-2.c
+++ b/gcc/testsuite/gcc.dg/torture/vector-2.c
@@ -1,5 +1,9 @@
 /* Check that vector insertion works correctly. */
 
+/* { dg-do run } */
+/* { dg-options "-msse" { target { i?86-*-* x86_64-*-* } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
 #define vector __attribute__((vector_size(16) ))
 
 vector int f0(vector int t, int a)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c
index f2ddab2..033c60d 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-tree-optimized -w" } */
+/* { dg-options "-O1 -fdump-tree-optimized -w -msse" { target { i?86-*-* x86_64-*-* } } } */
 
 #define vector __attribute__((vector_size(16) ))
 struct VecClass
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c b/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c
index 2442b93..599d1f1 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c
@@ -1,4 +1,5 @@
 /* { dg-options "-O2 -fdump-tree-fre -w" } */
+/* { dg-options "-O2 -fdump-tree-fre -w -msse" { target { i?86-*-* x86_64-*-* } } } */
 /* { dg-do compile } */
 #define vector __attribute__((vector_size(sizeof(int)*4) ))
 struct s { vector int i; };
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c b/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c
index 73a68f9..e6ca756 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-tree-optimized -w" } */
-/* Check that SRA replaces strucutres containing vectors. */
+/* { dg-options "-O1 -fdump-tree-optimized -w -msse" { target { i?86-*-* x86_64-*-* } } } */
+/* Check that SRA replaces structures containing vectors. */
 
 #define vector __attribute__((vector_size(16)))
 
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c b/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c
index 5b07c67..6fe0e87 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-w -O1 -fdump-tree-gimple" } */
+/* { dg-options "-w -O1 -fdump-tree-gimple -msse" { target { i?86-*-* x86_64-*-* } } } */
 
 
 /* We should be able to produce a BIT_FIELD_REF for each of these vector access. */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c b/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c
index cb68093..e34532d 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-w -O1 -fdump-tree-optimized" } */
+/* { dg-options "-w -O1 -fdump-tree-optimized -msse" { target { i?86-*-* x86_64-*-* } } } */
 
 #define vector __attribute__(( vector_size(16) ))
 
diff --git a/gcc/testsuite/gcc.target/i386/vect-args.c b/gcc/testsuite/gcc.target/i386/vect-args.c
index 94b602d..fc45889 100644
--- a/gcc/testsuite/gcc.target/i386/vect-args.c
+++ b/gcc/testsuite/gcc.target/i386/vect-args.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-w" } */
+/* { dg-options "-w -Wno-psabi" } */
 
 /* SSE1 and SSE2 modes.  */
 typedef unsigned char V16QImode __attribute__((vector_size(16)));