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| author | Alexandre Oliva <aoliva@cygnus.com> | 2000-04-23 23:28:39 +0000 |
|---|---|---|
| committer | Alexandre Oliva <aoliva@gcc.gnu.org> | 2000-04-23 23:28:39 +0000 |
| commit | 8b2cfbe6ea278ca20073a496b52a21032a9913e7 (patch) | |
| tree | 1004d644e4afcb83f86dec65b53c27c95af7d617 | |
| parent | 713f0303cc20449b51f013007d4247e0d2a22fac (diff) | |
| download | gcc-8b2cfbe6ea278ca20073a496b52a21032a9913e7.zip gcc-8b2cfbe6ea278ca20073a496b52a21032a9913e7.tar.gz gcc-8b2cfbe6ea278ca20073a496b52a21032a9913e7.tar.bz2 | |
mn10300.md (addsi): `inc4' on address registers does not modify cc...
* config/mn10300/mn10300.md (addsi): `inc4' on address
registers does not modify cc, but `inc' on an extended
register does.
From-SVN: r33363
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mn10300/mn10300.md | 15 |
2 files changed, 14 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9297006..8a9d54c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Sun Apr 23 20:16:49 2000 Alexandre Oliva <aoliva@cygnus.com> + + * config/mn10300/mn10300.md (addsi): `inc4' on address + registers does not modify cc, but `inc' on an extended + register does. + Sun Apr 23 16:24:35 2000 Denis Chertykov <denisc@overta.ru> * reload.c (find_equiv_reg): Checks all valueno regs diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index 80bd881..c2f74e7 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -760,9 +760,9 @@ }") (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax") - (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax") - (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))] + [(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,xy,!dax") + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax") + (match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))] "TARGET_AM33" "* { @@ -772,11 +772,12 @@ case 1: return \"inc %0\"; case 2: - return \"inc4 %0\"; case 3: + return \"inc4 %0\"; case 4: - return \"add %2,%0\"; case 5: + return \"add %2,%0\"; + case 6: { enum reg_class src1_class, src2_class, dst_class; @@ -835,10 +836,10 @@ abort (); } }" - [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")]) + [(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")]) (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax") + [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,xy,!dax") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax") (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))] "" |