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authorRenlin Li <renlin.li@arm.com>2015-11-12 10:14:35 +0000
committerRenlin Li <renlin@gcc.gnu.org>2015-11-12 10:14:35 +0000
commit87494f556989cda8c12041d0a6e242ca99b3c957 (patch)
treeaa796c9f8b5043e5fc52d4dd9bf8e65a6748e550
parent53dc6fb8622e89e4d83b06ec66ab6f7be492dd00 (diff)
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[PATCH][ARM]Fix addsi3_compare_op2 pattern.
gcc/ 2015-11-12 Renlin Li <renlin.li@arm.com> * config/arm/arm.md (addsi3_compare_op2): Make the order of assembly pattern consistent with constraint order. From-SVN: r230222
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/arm/arm.md4
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0b68dfa..db14b22 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-11-12 Renlin Li <renlin.li@arm.com>
+
+ * config/arm/arm.md (addsi3_compare_op2): Make the order of
+ assembly pattern consistent with constraint order.
+
2015-11-12 Tom de Vries <tom@codesourcery.com>
* gen-pass-instances.awk (handle_line): Simplify match regexp.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8ebb1bf..73c3088 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -747,8 +747,8 @@
"TARGET_32BIT"
"@
adds%?\\t%0, %1, %2
- adds%?\\t%0, %1, %2
- subs%?\\t%0, %1, #%n2"
+ subs%?\\t%0, %1, #%n2
+ adds%?\\t%0, %1, %2"
[(set_attr "conds" "set")
(set_attr "type" "alus_imm,alus_imm,alus_sreg")]
)