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| author | Joseph Myers <joseph@codesourcery.com> | 2011-02-16 22:57:55 +0000 |
|---|---|---|
| committer | Joseph Myers <jsm28@gcc.gnu.org> | 2011-02-16 22:57:55 +0000 |
| commit | 8226cd7b77ab46aabc22550acaf5be612e0d5a39 (patch) | |
| tree | a43e3f419b8ebe3cfd6be819371e8c12e9365275 | |
| parent | 8c53c3ae5aab9775e9464d010677d78e113715e3 (diff) | |
| download | gcc-8226cd7b77ab46aabc22550acaf5be612e0d5a39.zip gcc-8226cd7b77ab46aabc22550acaf5be612e0d5a39.tar.gz gcc-8226cd7b77ab46aabc22550acaf5be612e0d5a39.tar.bz2 | |
* config/m32c/m32c.h (LIB_SPEC): Match -msim not -msim*.
From-SVN: r170226
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c.h | 16 |
2 files changed, 12 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 241a28f..d00e6d5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2011-02-16 Joseph Myers <joseph@codesourcery.com> + * config/m32c/m32c.h (LIB_SPEC): Match -msim not -msim*. + +2011-02-16 Joseph Myers <joseph@codesourcery.com> + * config/lm32/lm32.h (ASM_SPEC): Use %{muser-enabled} instead of %{muser-extend-enabled}. diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h index 5c6970a..9cabeed 100644 --- a/gcc/config/m32c/m32c.h +++ b/gcc/config/m32c/m32c.h @@ -1,5 +1,5 @@ /* Target Definitions for R8C/M16C/M32C - Copyright (C) 2005, 2007, 2008, 2009, 2010 + Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. Contributed by Red Hat. @@ -54,13 +54,13 @@ family. Most of the logic here is making sure we do the right thing when no CPU is specified, which defaults to R8C. */ #undef LIB_SPEC -#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \ -%{msim*:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \ - %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \ -%{!T*:%{!msim*: %{mcpu=m16c:%Tm16c.ld} \ - %{mcpu=m32cm:%Tm32cm.ld} \ - %{mcpu=m32c:%Tm32c.ld} \ - %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \ +#define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \ +%{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \ + %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \ +%{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \ + %{mcpu=m32cm:%Tm32cm.ld} \ + %{mcpu=m32c:%Tm32c.ld} \ + %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \ " /* Run-time Target Specification */ |