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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-08-07 19:08:55 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-08-07 19:08:55 +0000 |
| commit | 801790b37ca817089ecbae214340162e6d94ea6a (patch) | |
| tree | 35bd16b516b6402219f067fbb2d825df2c4a1859 | |
| parent | b0760a40bef3ca690691bf5d214da95b5dc25266 (diff) | |
| download | gcc-801790b37ca817089ecbae214340162e6d94ea6a.zip gcc-801790b37ca817089ecbae214340162e6d94ea6a.tar.gz gcc-801790b37ca817089ecbae214340162e6d94ea6a.tar.bz2 | |
[AArch64] Prefer FPRs over GPRs for CLASTB
This patch makes the SVE CLASTB GPR alternative more expensive than the
FPR alternative in order to avoid unnecessary cross-file moves. It also
fixes the prefix used to print the FPR; <vw> only handles 32-bit and
64-bit elements.
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (fold_extract_last_<mode>):
Disparage the GPR alternative relative to the FPR one.
Fix handling of 8-bit and 16-bit FPR values.
gcc/testsuite/
* gcc.target/aarch64/sve/clastb_8.c: New test.
From-SVN: r274191
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c | 25 |
4 files changed, 37 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 43e53c0..31cbd59 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64-sve.md (fold_extract_last_<mode>): + Disparage the GPR alternative relative to the FPR one. + Fix handling of 8-bit and 16-bit FPR values. + +2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/iterators.md (BITWISEV): Delete. (SVE_INT_REDUCTION, SVE_FP_REDUCTION): New int iterators. (optab): Handle UNSPEC_UMAXV, UNSPEC_UMINV, UNSPEC_SMAXV, diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 3d60afa..41c92a0 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3104,7 +3104,7 @@ ;; Set operand 0 to the last active element in operand 3, or to tied ;; operand 1 if no elements are active. (define_insn "fold_extract_last_<mode>" - [(set (match_operand:<VEL> 0 "register_operand" "=r, w") + [(set (match_operand:<VEL> 0 "register_operand" "=?r, w") (unspec:<VEL> [(match_operand:<VEL> 1 "register_operand" "0, 0") (match_operand:<VPRED> 2 "register_operand" "Upl, Upl") @@ -3113,7 +3113,7 @@ "TARGET_SVE" "@ clastb\t%<vwcore>0, %2, %<vwcore>0, %3.<Vetype> - clastb\t%<vw>0, %2, %<vw>0, %3.<Vetype>" + clastb\t%<Vetype>0, %2, %<Vetype>0, %3.<Vetype>" ) ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a536398..dd37b72 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-08-07 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/sve/clastb_8.c: New test. + 2019-08-07 Uroš Bizjak <ubizjak@gmail.com> PR target/91385 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c new file mode 100644 index 0000000..d86a428 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c @@ -0,0 +1,25 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 --save-temps" } */ + +#include <stdint.h> + +#define TEST_TYPE(TYPE) \ + void \ + test_##TYPE (TYPE *ptr, TYPE *a, TYPE *b, TYPE min_v) \ + { \ + TYPE last = *ptr; \ + for (int i = 0; i < 1024; i++) \ + if (a[i] < min_v) \ + last = b[i]; \ + *ptr = last; \ + } + +TEST_TYPE (uint8_t); +TEST_TYPE (uint16_t); +TEST_TYPE (uint32_t); +TEST_TYPE (uint64_t); + +/* { dg-final { scan-assembler {\tclastb\t(b[0-9]+), p[0-7], \1, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(h[0-9]+), p[0-7], \1, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(s[0-9]+), p[0-7], \1, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(d[0-9]+), p[0-7], \1, z[0-9]+\.d\n} } } */ |