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authorRobert Suchanek <robert.suchanek@imgtec.com>2015-07-15 11:42:34 +0000
committerRobert Suchanek <rts@gcc.gnu.org>2015-07-15 11:42:34 +0000
commit6a2b848b31c45cc2e5d3371a4ed3e7b49ee7ae7e (patch)
treedf90e73e16ef62383eb76b546f8b6496a4f76fe6
parent22dd66d46a5212158999604ded5ccc6a9878125a (diff)
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Support interrupt handlers with hard-float.
gcc/ * config/mips/mips.c (mips_compute_frame_info): Allow -mhard-float in interrupt attribute. (mips_expand_prologue): Disable the floating point unit in an ISR. * config/mips/mips.h (SR_COP1): New define. From-SVN: r225818
-rw-r--r--gcc/ChangeLog7
-rw-r--r--gcc/config/mips/mips.c10
-rw-r--r--gcc/config/mips/mips.h2
3 files changed, 17 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 44fa51a..84574f0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-07-15 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * config/mips/mips.c (mips_compute_frame_info): Allow -mhard-float in
+ interrupt attribute.
+ (mips_expand_prologue): Disable the floating point unit in an ISR.
+ * config/mips/mips.h (SR_COP1): New define.
+
2015-07-15 Richard Biener <rguenther@suse.de>
* genmatch.c (parser::peek, parser::peek_ident): Add argument
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 26c2ba8..671fed8 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -10254,8 +10254,6 @@ mips_compute_frame_info (void)
{
if (mips_isa_rev < 2)
error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
- else if (TARGET_HARD_FLOAT)
- error ("the %<interrupt%> attribute requires %<-msoft-float%>");
else if (TARGET_MIPS16)
error ("interrupt handlers cannot be MIPS16 functions");
else
@@ -11495,6 +11493,14 @@ mips_expand_prologue (void)
GEN_INT (5),
GEN_INT (SR_IE),
gen_rtx_REG (SImode, GP_REG_FIRST)));
+
+ if (TARGET_HARD_FLOAT)
+ /* Disable COP1 for hard-float. This will lead to an exception
+ if floating-point code is executed in an ISR. */
+ emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+ GEN_INT (1),
+ GEN_INT (SR_COP1),
+ gen_rtx_REG (SImode, GP_REG_FIRST)));
}
else
{
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 37c85f0..9d10a28 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1807,6 +1807,8 @@ FP_ASM_SPEC "\
/* Request Interrupt Priority Level is from bit 10 to bit 15 of
the cause register for the EIC interrupt mode. */
#define CAUSE_IPL 10
+/* COP1 Enable is at bit 29 of the status register. */
+#define SR_COP1 29
/* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
#define SR_IPL 10
/* Exception Level is at bit 1 of the status register. */