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| author | David Edelsohn <edelsohn@gnu.org> | 1996-02-27 21:39:16 +0000 |
|---|---|---|
| committer | David Edelsohn <edelsohn@gnu.org> | 1996-02-27 21:39:16 +0000 |
| commit | 685f39066bb11fba9434c10d21c98a29e51d9093 (patch) | |
| tree | b7dcaeebeef9744d7fe73b79eefc4d4645926fc2 | |
| parent | 92fd61996f017e94d3a3a79b743f2f3617952a52 (diff) | |
| download | gcc-685f39066bb11fba9434c10d21c98a29e51d9093.zip gcc-685f39066bb11fba9434c10d21c98a29e51d9093.tar.gz gcc-685f39066bb11fba9434c10d21c98a29e51d9093.tar.bz2 | |
DImode insv and extzv, movsf split
From-SVN: r11356
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 92 |
1 files changed, 89 insertions, 3 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fec54cc..6a22c99 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2147,6 +2147,22 @@ return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\"; }") +(define_insn "" + [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") + (match_operand:DI 1 "const_int_operand" "i") + (match_operand:DI 2 "const_int_operand" "i")) + (match_operand:DI 3 "gpc_reg_operand" "r"))] + "TARGET_POWERPC64" + "* +{ + int start = INTVAL (operands[2]) & 63; + int size = INTVAL (operands[1]) & 63; + + operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - start - size); + operands[1] = gen_rtx (CONST_INT, VOIDmode, start); + return \"rldimi %0,%3,%2,%1\"; +}") + (define_expand "extzv" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") @@ -2247,6 +2263,68 @@ }" [(set_attr "type" "delayed_compare")]) +(define_insn "" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "i") + (match_operand:DI 3 "const_int_operand" "i")))] + "TARGET_POWERPC64" + "* +{ + int start = INTVAL (operands[3]) & 63; + int size = INTVAL (operands[2]) & 63; + + if (start + size >= 64) + operands[3] = const0_rtx; + else + operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); + operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size); + return \"rldicl %0,%1,%3,%2\"; +}") + +(define_insn "" + [(set (match_operand:CC 0 "gpc_reg_operand" "=x") + (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "i") + (match_operand:DI 3 "const_int_operand" "i")) + (const_int 0))) + (clobber (match_scratch:DI 4 "=r"))] + "TARGET_POWERPC64" + "* +{ + int start = INTVAL (operands[3]) & 63; + int size = INTVAL (operands[2]) & 63; + + if (start + size >= 64) + operands[3] = const0_rtx; + else + operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); + operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size); + return \"rldicl. %4,%1,%3,%2\"; +}") + +(define_insn "" + [(set (match_operand:CC 4 "gpc_reg_operand" "=x") + (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "const_int_operand" "i") + (match_operand:DI 3 "const_int_operand" "i")) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") + (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] + "TARGET_POWERPC64" + "* +{ + int start = INTVAL (operands[3]) & 63; + int size = INTVAL (operands[2]) & 63; + + if (start + size >= 64) + operands[3] = const0_rtx; + else + operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); + operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size); + return \"rldicl. %0,%1,%3,%2\"; +}") + (define_insn "rotlsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") @@ -5102,8 +5180,16 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "") (match_operand:SF 1 "easy_fp_constant" ""))] "reload_completed && REGNO (operands[0]) <= 31" - [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] - "") + [(set (subreg:SI (match_dup 0) 0) (match_dup 2))] + " +{ + long l; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (rv, l); + operands[2] = GEN_INT(l); +}") (define_insn "" [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") @@ -5181,7 +5267,7 @@ (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "easy_fp_constant" ""))] + (match_operand:DF 1 "easy_fp_constant" ""))] "TARGET_64BIT && reload_completed && REGNO (operands[0]) <= 31" [(set (subreg:DI (match_dup 0) 0) (subreg:DI (match_dup 1) 0))] "") |