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| author | H.J. Lu <hjl@gcc.gnu.org> | 2017-09-24 14:37:09 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2017-09-24 14:37:09 -0700 |
| commit | 60ba7cd38dff1e64ffcfac04665e32caebcbe6fe (patch) | |
| tree | 76217d8b67ea08f88b76beb8c62b38c2d7d8f795 | |
| parent | c6c74708b0cc313c90ab5bffc0c2eaa6062827cb (diff) | |
| download | gcc-60ba7cd38dff1e64ffcfac04665e32caebcbe6fe.zip gcc-60ba7cd38dff1e64ffcfac04665e32caebcbe6fe.tar.gz gcc-60ba7cd38dff1e64ffcfac04665e32caebcbe6fe.tar.bz2 | |
x32: Encode %esp as %rsp to avoid 0x67 prefix
Since the upper 32 bits of stack register are always zero for x32, we
can encode %esp as %rsp to avoid 0x67 prefix in address if there is no
index or base register.
gcc/
PR target/82267
* config/i386/i386.c (ix86_print_operand_address_as): Encode
%esp as %rsp to avoid 0x67 prefix if there is no index or base
register.
gcc/testsuite/
PR target/82267
* gcc.target/i386/pr82267.c: New test.
From-SVN: r253127
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr82267.c | 14 |
4 files changed, 34 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 041e47f..b92347e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-09-24 Uros Bizjak <ubizjak@gmail.com> + + PR target/82267 + * config/i386/i386.c (ix86_print_operand_address_as): Encode + %esp as %rsp to avoid 0x67 prefix if there is no index or base + register. + 2017-09-23 Uros Bizjak <ubizjak@gmail.com> PR bootstrap/82306 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7434aae..293287c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19953,6 +19953,14 @@ ix86_print_operand_address_as (FILE *file, rtx addr, code = 'k'; } + /* Since the upper 32 bits of RSP are always zero for x32, we can + encode %esp as %rsp to avoid 0x67 prefix if there is no index or + base register. */ + if (TARGET_X32 && Pmode == SImode + && ((!index && base && REGNO (base) == SP_REG) + || (!base && index && REGNO (index) == SP_REG))) + code = 'q'; + if (ASSEMBLER_DIALECT == ASM_ATT) { if (disp) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 21e6e2d..18c4a26 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-09-24 H.J. Lu <hongjiu.lu@intel.com> + + PR target/82267 + * gcc.target/i386/pr82267.c: New test. + 2017-09-24 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/66328 diff --git a/gcc/testsuite/gcc.target/i386/pr82267.c b/gcc/testsuite/gcc.target/i386/pr82267.c new file mode 100644 index 0000000..5e4b271 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr82267.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mx32 -maddress-mode=short" } */ + +int +stackuse (void) +{ + volatile int foo = 2; + return foo * 3; +} + +/* Verify we that use %rsp to access stack. */ +/* { dg-final { scan-assembler-not "%esp" } } */ +/* { dg-final { scan-assembler "%rsp" } } */ |