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| author | Kirill Yukhin <kirill.yukhin@intel.com> | 2016-05-18 09:16:09 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2016-05-18 09:16:09 +0000 |
| commit | 5ae46837e197be9b99bc8ada79f37f1a7dd4b51f (patch) | |
| tree | 2fea57c0083cc8c16522646460e093731f5e4095 | |
| parent | 188940605054262324b8d268364f26cd05370327 (diff) | |
| download | gcc-5ae46837e197be9b99bc8ada79f37f1a7dd4b51f.zip gcc-5ae46837e197be9b99bc8ada79f37f1a7dd4b51f.tar.gz gcc-5ae46837e197be9b99bc8ada79f37f1a7dd4b51f.tar.bz2 | |
i386. Extend static buffers. Fix SF mode operand constraint to `Yv' in storehpd pattern.
gcc/
* gcc/config/i386/sse.md (define_insn "*andnot<mode>3"): Extend static
array to 128 chars.
(define_insn "*andnottf3"): Ditto.
(define_insn "*<code><mode>3"/any_logic): Ditto.
(define_insn "*<code>tf3"/any_logic): Ditto.
(define_insn "sse2_storehpd"): Use Yv constraint for scalar
operand to block AVX-512VL insn variant emit when it is not enabled.
From-SVN: r236364
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 12 |
2 files changed, 16 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c5376a1..4592bcc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,15 @@ 2016-05-18 Kirill Yukhin <kirill.yukhin@intel.com> + * gcc/config/i386/sse.md (define_insn "*andnot<mode>3"): Extend static + array to 128 chars. + (define_insn "*andnottf3"): Ditto. + (define_insn "*<code><mode>3"/any_logic): Ditto. + (define_insn "*<code>tf3"/any_logic): Ditto. + (define_insn "sse2_storehpd"): Use Yv constraint for scalar + operand to block AVX-512VL insn variant emit when it is not enabled. + +2016-05-18 Kirill Yukhin <kirill.yukhin@intel.com> + * config/i386/sse.md (define_insn "*vec_concatv2sf_sse4_1"): Use 'Yv' constraint fot SF mode. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a8492c7..b0d3f81 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3027,7 +3027,7 @@ (match_operand:MODEF 2 "register_operand" "x,x,v,v")))] "SSE_FLOAT_MODE_P (<MODE>mode)" { - static char buf[32]; + static char buf[128]; const char *ops; const char *suffix = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>"; @@ -3094,7 +3094,7 @@ (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))] "TARGET_SSE" { - static char buf[32]; + static char buf[128]; const char *ops; const char *tmp = (which_alternative >= 2 ? "pandnq" @@ -3150,7 +3150,7 @@ (match_operand:MODEF 2 "register_operand" "x,x,v,v")))] "SSE_FLOAT_MODE_P (<MODE>mode)" { - static char buf[32]; + static char buf[128]; const char *ops; const char *suffix = (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>"; @@ -3225,7 +3225,7 @@ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, TFmode, operands)" { - static char buf[32]; + static char buf[128]; const char *ops; const char *tmp = (which_alternative >= 2 ? "p<logic>q" @@ -8426,9 +8426,9 @@ ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_storehpd" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r") + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,Yv,x,*f,r") (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o") + (match_operand:V2DF 1 "nonimmediate_operand" " v,0, v,o,o,o") (parallel [(const_int 1)])))] "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ |