aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTamar Christina <tamar.christina@arm.com>2017-10-05 15:17:39 +0000
committerTamar Christina <tnfchris@gcc.gnu.org>2017-10-05 15:17:39 +0000
commit592fbfb5fb376972c21d88ac57b0a4a38018e79f (patch)
tree6d9f349b4ed51457480f7641b70972032810c6ae
parent0322303e26cc317970fa311c032121078dab51dc (diff)
downloadgcc-592fbfb5fb376972c21d88ac57b0a4a38018e79f.zip
gcc-592fbfb5fb376972c21d88ac57b0a4a38018e79f.tar.gz
gcc-592fbfb5fb376972c21d88ac57b0a4a38018e79f.tar.bz2
slp-perm-9.c: Use vect_sizes_16B_8B.
gcc/testsuite/ 2017-10-05 Tamar Christina <tamar.christina@arm.com> * gcc.dg/vect/slp-perm-9.c: Use vect_sizes_16B_8B. * lib/target-supports.exp (vect_sizes_16B_8B): New. gcc/ 2017-10-05 Tamar Christina <tamar.christina@arm.com> * doc/sourcebuild.texi (vect_sizes_16B_8B, vect_sizes_32B_16B): New. From-SVN: r253452
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/doc/sourcebuild.texi6
-rw-r--r--gcc/testsuite/ChangeLog7
-rw-r--r--gcc/testsuite/gcc.dg/vect/slp-perm-9.c4
-rw-r--r--gcc/testsuite/lib/target-supports.exp13
5 files changed, 31 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 43bb147..777340c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2017-10-05 Tamar Christina <tamar.christina@arm.com>
+
+ * doc/sourcebuild.texi (vect_sizes_16B_8B, vect_sizes_32B_16B): New.
+
2017-10-05 Jan Hubicka <hubicka@ucw.cz>
* i386.c (znver1_cost): Set branch_cost to 3 (instead of 2)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 1646d0a..a2f0429 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1519,6 +1519,12 @@ Target supports conversion from @code{double} to @code{signed int}.
@item vect_max_reduc
Target supports max reduction for vectors.
+
+@item vect_sizes_16B_8B
+Target supports 16- and 8-bytes vectors.
+
+@item vect_sizes_32B_16B
+Target supports 32- and 16-bytes vectors.
@end table
@subsubsection Thread Local Storage attributes
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index bfb82c0..5b7919fc 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,4 +1,9 @@
-2017-09-28 Tamar Christina <tamar.christina@arm.com>
+2017-10-05 Tamar Christina <tamar.christina@arm.com>
+
+ * gcc.dg/vect/slp-perm-9.c: Use vect_sizes_16B_8B.
+ * lib/target-supports.exp (vect_sizes_16B_8B): New.
+
+2017-10-05 Tamar Christina <tamar.christina@arm.com>
* gcc.dg/vect/vect-align-1.c: Fix vect_hw_misalign condition.
* gcc.dg/vect/vect-align-2.c: Likewise.
diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c
index 4d9c11d..b9b5a3b 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c
@@ -54,8 +54,8 @@ int main (int argc, const char* argv[])
return 0;
}
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_16B_8B } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_16B_8B } } } } } */
/* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target vect_perm_short } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */
/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b6f9e51..fbe8f2a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7671,6 +7671,19 @@ proc check_effective_target_vect_sizes_32B_16B { } {
}
}
+# Return true if 16- and 8-bytes vectors are available.
+
+proc check_effective_target_vect_sizes_16B_8B { } {
+ if { [check_avx_available]
+ || [is-effective-target arm_neon]
+ || [istarget aarch64*-*-*] } {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+
# Return true if 128-bits vectors are preferred even if 256-bits vectors
# are available.