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| author | Zhenqiang Chen <zhenqiang.chen@linaro.org> | 2012-10-19 09:24:39 +0000 |
|---|---|---|
| committer | Xuepeng Guo <xguo@gcc.gnu.org> | 2012-10-19 09:24:39 +0000 |
| commit | 57fc62cb326ab913d7eef6d0ac0cd7788edd1797 (patch) | |
| tree | 8919ecc2537c84ca7a9c3e262c47f0ad343aff1d | |
| parent | c8379865b38e7dfdd18d1aa64bb95ed76c7b54f0 (diff) | |
| download | gcc-57fc62cb326ab913d7eef6d0ac0cd7788edd1797.zip gcc-57fc62cb326ab913d7eef6d0ac0cd7788edd1797.tar.gz gcc-57fc62cb326ab913d7eef6d0ac0cd7788edd1797.tar.bz2 | |
re PR target/54892 (, ICE in extract_insn, at recog.c:2123)
gcc/ChangeLog
PR target/54892
* config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make
sure the mode is correct when falling through from above cases.
gcc/testsuite/ChangeLog
PR target/54892
* gcc.target/arm/pr54892.c: New.
From-SVN: r192609
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr54892.c | 7 |
4 files changed, 20 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9b09aaa..cdba336 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + PR target/54892 + * config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make + sure the mode is correct when falling through from above cases. + 2012-10-19 Bin Cheng <bin.cheng@arm.com> * common.opt (flag_ira_hoist_pressure): New. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 327ef22..11f793d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -25447,8 +25447,8 @@ arm_expand_compare_and_swap (rtx operands[]) case SImode: /* Force the value into a register if needed. We waited until after the zero-extension above to do this properly. */ - if (!arm_add_operand (oldval, mode)) - oldval = force_reg (mode, oldval); + if (!arm_add_operand (oldval, SImode)) + oldval = force_reg (SImode, oldval); break; case DImode: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 57d4383..4af8265 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + PR target/54892 + * gcc.target/arm/pr54892.c: New. + 2012-10-19 Bin Cheng <bin.cheng@arm.com> * testsuite/gcc.dg/hoist-register-pressure.c: New test. diff --git a/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc/testsuite/gcc.target/arm/pr54892.c new file mode 100644 index 0000000..a7fe1bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr54892.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +int set_role(unsigned char role_id, short m_role) +{ + return __sync_bool_compare_and_swap(&m_role, -1, role_id); +} + |