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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-09-26 18:50:23 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-09-26 18:50:23 +0000 |
| commit | 57e6b981a37579907ae8a63aef3a78fa76cadfb8 (patch) | |
| tree | e1b3f5f7bfb2c2598e4d5f230756edb824e4dd6c | |
| parent | 2f448503d619f753f0bd6ecb1ac95e36bd080f1e (diff) | |
| download | gcc-57e6b981a37579907ae8a63aef3a78fa76cadfb8.zip gcc-57e6b981a37579907ae8a63aef3a78fa76cadfb8.tar.gz gcc-57e6b981a37579907ae8a63aef3a78fa76cadfb8.tar.bz2 | |
vsx.md (vsx_xscvdpspn): Eliminate useless alternative constraint.
2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless
alternative constraint.
(vsx_xscvspdpn): Likewise.
(vsx_xscvspdpn_scalar): Likewise.
From-SVN: r253213
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 14 |
2 files changed, 12 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 75ca6db..54acc78 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -16,6 +16,11 @@ instruction instead of FRSP and XSCVDPSPN. * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that it is adjacent to the other XSCVSPDP insns. + (vsx_xscvdpsp_scalar): Use "ww" constraint instead of "f" to allow + SFmode to be in traditional Altivec registers. + (vsx_xscvdpspn): Eliminate useless alternative constraint. + (vsx_xscvspdpn): Likewise. + (vsx_xscvspdpn_scalar): Likewise. 2017-09-26 Martin Jambor <mjambor@suse.cz> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 3c54d4a..e21801a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1803,7 +1803,7 @@ ;; format of scalars is actually DF. (define_insn "vsx_xscvdpsp_scalar" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")] + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (V4SFmode)" "xscvdpsp %x0,%x1" @@ -1811,24 +1811,24 @@ ;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs (define_insn "vsx_xscvdpspn" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww") - (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")] + [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww") + (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "ws")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" "xscvdpspn %x0,%x1" [(set_attr "type" "fp")]) (define_insn "vsx_xscvspdpn" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) (define_insn "vsx_xscvdpspn_scalar" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")] + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" "xscvdpspn %x0,%x1" |