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| author | Sylvia Taylor <sylvia.taylor@arm.com> | 2019-05-30 17:36:52 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-05-30 17:36:52 +0000 |
| commit | 3db85990dbde7f9c8212fe0fb8a241c5d2993198 (patch) | |
| tree | 1b4fb0d12fb2c8f090d63a6da6f00b79b3467372 | |
| parent | c9c41a6b1bf681e319b3b3df035eeb9ad754ea0d (diff) | |
| download | gcc-3db85990dbde7f9c8212fe0fb8a241c5d2993198.zip gcc-3db85990dbde7f9c8212fe0fb8a241c5d2993198.tar.gz gcc-3db85990dbde7f9c8212fe0fb8a241c5d2993198.tar.bz2 | |
[aarch64]: add support for fabd in sve
This patch adds support in SVE to combine:
- fsub and fabs into fabd
fsub z0.s, z0.s, z1.s
fabs z0.s, p1/m, z0.s
---
fabd z0.s, p1/m, z0.s, z1.s
2019-05-30 Sylvia Taylor <sylvia.taylor@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*fabd<mode>3): New.
gcc/testsuite/
* gcc.target/aarch64/sve/fabd_1.c: New.
From-SVN: r271785
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 13 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/fabd_1.c | 35 |
4 files changed, 56 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c912da6..caee629 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2019-05-30 Sylvia Taylor <sylvia.taylor@arm.com> + + * config/aarch64/aarch64-sve.md (*fabd<mode>3): New. + 2019-05-30 Bill Schmidt <wschmidt@linux.ibm.com> Michael Meissner <meissner@linux.ibm.com> diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index b9cb1fa..2550586 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2528,6 +2528,19 @@ "<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>" ) +(define_insn "*fabd<mode>3" + [(set (match_operand:SVE_F 0 "register_operand" "=w") + (unspec:SVE_F + [(match_operand:<VPRED> 1 "register_operand" "Upl") + (abs:SVE_F + (minus:SVE_F + (match_operand:SVE_F 2 "register_operand" "0") + (match_operand:SVE_F 3 "register_operand" "w")))] + UNSPEC_MERGE_PTRUE))] + "TARGET_SVE" + "fabd\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>" +) + ;; Unpredicated FRINTy. (define_expand "<frint_pattern><mode>2" [(set (match_operand:SVE_F 0 "register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 92679459..1d8b3e8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-05-30 Sylvia Taylor <sylvia.taylor@arm.com> + + * gcc.target/aarch64/sve/fabd_1.c: New. + 2019-05-30 Iain Sandoe <iain@sandoe.co.uk> * gcc.target/i386/pr86257.c: Require native TLS support. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fabd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fabd_1.c new file mode 100644 index 0000000..13ad83b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/fabd_1.c @@ -0,0 +1,35 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O3 --save-temps" } */ + +#define N 16 + +typedef float *__restrict__ vnx4sf; +typedef double *__restrict__ vnx2df; +typedef _Float16 *__restrict__ vnx8hf_a; +typedef __fp16 *__restrict__ vnx8hf_b; + +extern float fabsf (float); +extern double fabs (double); + +#define FABD(type, abs, n) \ + void fabd_##type (type res, type a, type b) \ + { \ + int i; \ + for (i = 0; i < n; i++) \ + res[i] = abs (a[i] - b[i]); \ + } + +#define TEST_SVE_F_MODES(FUNC) \ + FUNC (vnx2df, fabs, N) \ + FUNC (vnx4sf, fabsf, N) \ + FUNC (vnx8hf_a, fabsf, N) \ + FUNC (vnx8hf_b, fabsf, N) \ + +TEST_SVE_F_MODES (FABD) + +/* { dg-final { scan-assembler "fabd" } } */ +/* { dg-final { scan-assembler-not "fsub" } } */ +/* { dg-final { scan-assembler-not "fabs" } } */ +/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ |