[AArch64] Implement some vca*_f[32,64] intrinsics.

	* config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
	(vcagt_f64): Likewise.
	(vcale_f64): Likewise.
	(vcaled_f64): Likewise.
	(vcales_f32): Likewise.
	(vcalt_f64): Likewise.
	(vcaltd_f64): Likewise.
	(vcalts_f32): Likewise.

	* gcc.target/aarch64/simd/vcage_f64.c: New test.
	* gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcale_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcales_f32.c: Likewise.
	* gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
	* gcc.target/aarch64/simd/vcalts_f32.c: Likewise.

From-SVN: r212196

11 files changed, 366 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 14d1909..a2d97ef 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2014-07-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/arm_neon.h (vcage_f64): New intrinsic.
+	(vcagt_f64): Likewise.
+	(vcale_f64): Likewise.
+	(vcaled_f64): Likewise.
+	(vcales_f32): Likewise.
+	(vcalt_f64): Likewise.
+	(vcaltd_f64): Likewise.
+	(vcalts_f32): Likewise.
+
 2014-07-01  Marek Polacek  <polacek@redhat.com>
 
 	* doc/invoke.texi: Document -Wint-conversion.
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index d5d8c23..83ac5e9 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -13823,6 +13823,12 @@ vaesimcq_u8 (uint8x16_t data)
 
 /* vcage  */
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcage_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) >= vabs_f64 (__b);
+}
+
 __extension__ static __inline uint32_t __attribute__ ((__always_inline__))
 vcages_f32 (float32_t __a, float32_t __b)
 {
@@ -13867,6 +13873,12 @@ vcagt_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) > vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcagt_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) > vabs_f64 (__b);
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcagtq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13893,6 +13905,24 @@ vcale_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) <= vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcale_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) <= vabs_f64 (__b);
+}
+
+__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+vcaled_f64 (float64_t __a, float64_t __b)
+{
+  return __builtin_fabs (__a) <= __builtin_fabs (__b) ? -1 : 0;
+}
+
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+vcales_f32 (float32_t __a, float32_t __b)
+{
+  return __builtin_fabsf (__a) <= __builtin_fabsf (__b) ? -1 : 0;
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcaleq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13913,6 +13943,18 @@ vcalt_f32 (float32x2_t __a, float32x2_t __b)
   return vabs_f32 (__a) < vabs_f32 (__b);
 }
 
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcalt_f64 (float64x1_t __a, float64x1_t __b)
+{
+  return vabs_f64 (__a) < vabs_f64 (__b);
+}
+
+__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
+vcaltd_f64 (float64_t __a, float64_t __b)
+{
+  return __builtin_fabs (__a) < __builtin_fabs (__b) ? -1 : 0;
+}
+
 __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
 vcaltq_f32 (float32x4_t __a, float32x4_t __b)
 {
@@ -13925,6 +13967,12 @@ vcaltq_f64 (float64x2_t __a, float64x2_t __b)
   return vabsq_f64 (__a) < vabsq_f64 (__b);
 }
 
+__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
+vcalts_f32 (float32_t __a, float32_t __b)
+{
+  return __builtin_fabsf (__a) < __builtin_fabsf (__b) ? -1 : 0;
+}
+
 /* vceq - vector.  */
 
 __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fd72e05..e12393c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2014-07-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/simd/vcage_f64.c: New test.
+	* gcc.target/aarch64/simd/vcagt_f64.c: Likewise.
+	* gcc.target/aarch64/simd/vcale_f64.c: Likewise.
+	* gcc.target/aarch64/simd/vcaled_f64.c: Likewise.
+	* gcc.target/aarch64/simd/vcales_f32.c: Likewise.
+	* gcc.target/aarch64/simd/vcalt_f64.c: Likewise.
+	* gcc.target/aarch64/simd/vcaltd_f64.c: Likewise.
+	* gcc.target/aarch64/simd/vcalts_f32.c: Likewise.
+
 2014-07-01  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	* g++.dg/cpp1y/pr59867.C: Fix target selector.
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c
new file mode 100644
index 0000000..7ddef58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcage_f64.c
@@ -0,0 +1,38 @@
+/* Test the vcage_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) >= __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcage_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c
new file mode 100644
index 0000000..df6911a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcagt_f64.c
@@ -0,0 +1,38 @@
+/* Test the vcagt_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) > __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcagt_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c
new file mode 100644
index 0000000..574bfea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcale_f64.c
@@ -0,0 +1,38 @@
+/* Test the vcale_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcale_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
new file mode 100644
index 0000000..9ea31d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaled_f64.c
@@ -0,0 +1,36 @@
+/* Test the vcaled_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcaled_f64 (in[i], in[j]);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
new file mode 100644
index 0000000..a69a096
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcales_f32.c
@@ -0,0 +1,36 @@
+/* Test the vcales_f32 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint32_t expected;
+  uint32_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) <= __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcales_f32 (in[i], in[j]);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facge\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c
new file mode 100644
index 0000000..d5bf5f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcalt_f64.c
@@ -0,0 +1,38 @@
+/* Test the vcalt_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+  float64x1_t arg1, arg2;
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        arg1 = (float64x1_t) { in[i] };
+        arg2 = (float64x1_t) { in[j] };
+        actual = vget_lane_u64 (vcalt_f64 (arg1, arg2), 0);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
new file mode 100644
index 0000000..fcdd75b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcaltd_f64.c
@@ -0,0 +1,36 @@
+/* Test the vcaltd_f64 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float64_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint64_t expected;
+  uint64_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcaltd_f64 (in[i], in[j]);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
new file mode 100644
index 0000000..0799dd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcalts_f32.c
@@ -0,0 +1,36 @@
+/* Test the vcalts_f32 AArch64 SIMD intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+#define SIZE 6
+
+extern void abort (void);
+
+volatile float32_t in[SIZE] = { -10.4, -3.14, 0.0, 1.5, 5.3, 532.3 };
+
+int
+main (void)
+{
+  uint32_t expected;
+  uint32_t actual;
+
+  int i, j;
+
+  for (i = 0; i < SIZE; ++i)
+   for (j = 0; j < SIZE; ++j)
+     {
+        expected = __builtin_fabs (in[i]) < __builtin_fabs (in[j]) ? -1 : 0;
+        actual = vcalts_f32 (in[i], in[j]);
+
+        if (actual != expected)
+          abort ();
+     }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "facgt\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+\n" } } */
+/* { dg-final { cleanup-saved-temps } } */