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| author | Richard Biener <rguenther@suse.de> | 2022-04-20 10:17:24 +0200 |
|---|---|---|
| committer | Richard Biener <rguenther@suse.de> | 2022-04-20 13:27:24 +0200 |
| commit | 36f1de95a61132f63c0c07ef154abd9f435721ac (patch) | |
| tree | fe13b569b1add4fa1843e7ef2c1c239328da5f09 | |
| parent | 0707f4280907c395b543464175411f8155817a9e (diff) | |
| download | gcc-36f1de95a61132f63c0c07ef154abd9f435721ac.zip gcc-36f1de95a61132f63c0c07ef154abd9f435721ac.tar.gz gcc-36f1de95a61132f63c0c07ef154abd9f435721ac.tar.bz2 | |
tree-optimization/105312 - fix ISEL VCOND expansion
The following aligns ISEL VEC_COND_EXPR expansion using VCOND
with the optab query done by vector lowering. Instead of only
allowing the signed optab to provide EQ/NE compares we allow both
here though since there seems to be no documented canonicalization.
2022-04-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/105312
* gimple-isel.cc (gimple_expand_vec_cond_expr): Query both
VCOND and VCONDU for EQ and NE.
* gcc.target/arm/pr105312.c: New testcase.
| -rw-r--r-- | gcc/gimple-isel.cc | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr105312.c | 23 |
2 files changed, 31 insertions, 0 deletions
diff --git a/gcc/gimple-isel.cc b/gcc/gimple-isel.cc index 3635585..a8f7a0d 100644 --- a/gcc/gimple-isel.cc +++ b/gcc/gimple-isel.cc @@ -245,6 +245,14 @@ gimple_expand_vec_cond_expr (struct function *fun, gimple_stmt_iterator *gsi, GET_MODE_NUNITS (cmp_op_mode))); icode = get_vcond_icode (mode, cmp_op_mode, unsignedp); + /* Some targets do not have vcondeq and only vcond with NE/EQ + but not vcondu, so make sure to also try vcond here as + vcond_icode_p would canonicalize the optab query to. */ + if (icode == CODE_FOR_nothing + && (tcode == NE_EXPR || tcode == EQ_EXPR) + && ((icode = get_vcond_icode (mode, cmp_op_mode, !unsignedp)) + != CODE_FOR_nothing)) + unsignedp = !unsignedp; if (icode == CODE_FOR_nothing) { if (tcode == LT_EXPR diff --git a/gcc/testsuite/gcc.target/arm/pr105312.c b/gcc/testsuite/gcc.target/arm/pr105312.c new file mode 100644 index 0000000..a02831b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr105312.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-mcpu=cortex-a15" } */ +/* { dg-add-options arm_neon } */ + +typedef float stress_matrix_type_t; +typedef unsigned int size_t; +static void __attribute__((optimize("-O3"))) stress_matrix_xy_identity( + const size_t n, + stress_matrix_type_t a[restrict n][n], + stress_matrix_type_t b[restrict n][n], + stress_matrix_type_t r[restrict n][n]) +{ + register size_t i; + (void)a; + (void)b; + for (i = 0; i < n; i++) { + register size_t j; + for (j = 0; j < n; j++) + r[i][j] = (i == j) ? 1.0 : 0.0; + return; + } +} |