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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-02-16 22:16:04 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-02-16 14:16:04 -0800 |
| commit | 2f3d266045f011f445c42d3218fed78581f8c8c4 (patch) | |
| tree | 684877f0553b64ff33acd6f9ed842aed0cdebecd | |
| parent | 49be11f5c9376c0b3ee0b4f8a1cc19ca797e9f45 (diff) | |
| download | gcc-2f3d266045f011f445c42d3218fed78581f8c8c4.zip gcc-2f3d266045f011f445c42d3218fed78581f8c8c4.tar.gz gcc-2f3d266045f011f445c42d3218fed78581f8c8c4.tar.bz2 | |
i386: Add ssse3_pmulhrswv4hi3 expander
There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require
AVX2.
PR target/89372
* config/i386/sse.md (ssedoublemode): Remove V4HI.
(PMULHRSW): Likewise.
(<ssse3_avx2>_pmulhrsw<mode>3): Require TARGET_SSSE3, not
TARGET_AVX2.
(ssse3_pmulhrswv4hi3): New expander.
From-SVN: r268964
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 26 |
2 files changed, 32 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 58e991d..d80e4f4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2019-02-16 H.J. Lu <hongjiu.lu@intel.com> + PR target/89372 + * config/i386/sse.md (ssedoublemode): Remove V4HI. + (PMULHRSW): Likewise. + (<ssse3_avx2>_pmulhrsw<mode>3): Require TARGET_SSSE3, not + TARGET_AVX2. + (ssse3_pmulhrswv4hi3): New expander. + +2019-02-16 H.J. Lu <hongjiu.lu@intel.com> + * config/i386/mmx.md (*vec_extractv2si_zext_mem): Doesn't require MMX. Add isa attribute. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8281fe2..8036136 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -596,7 +596,7 @@ [(V4SF "V8SF") (V8SF "V16SF") (V16SF "V32SF") (V2DF "V4DF") (V4DF "V8DF") (V8DF "V16DF") (V16QI "V16HI") (V32QI "V32HI") (V64QI "V64HI") - (V4HI "V4SI") (V8HI "V8SI") (V16HI "V16SI") (V32HI "V32SI") + (V8HI "V8SI") (V16HI "V16SI") (V32HI "V32SI") (V4SI "V4DI") (V8SI "V16SI") (V16SI "V32SI") (V4DI "V8DI") (V8DI "V16DI")]) @@ -15590,7 +15590,7 @@ (set_attr "mode" "DI")]) (define_mode_iterator PMULHRSW - [V4HI V8HI (V16HI "TARGET_AVX2")]) + [V8HI (V16HI "TARGET_AVX2")]) (define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask" [(set (match_operand:PMULHRSW 0 "register_operand") @@ -15629,7 +15629,7 @@ (const_int 14)) (match_dup 3)) (const_int 1))))] - "TARGET_AVX2" + "TARGET_SSSE3" { operands[3] = CONST1_RTX(<MODE>mode); ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands); @@ -15662,6 +15662,26 @@ (set_attr "prefix" "orig,maybe_evex,evex") (set_attr "mode" "<sseinsnmode>")]) +(define_expand "ssse3_pmulhrswv4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (truncate:V4HI + (lshiftrt:V4SI + (plus:V4SI + (lshiftrt:V4SI + (mult:V4SI + (sign_extend:V4SI + (match_operand:V4HI 1 "nonimmediate_operand")) + (sign_extend:V4SI + (match_operand:V4HI 2 "nonimmediate_operand"))) + (const_int 14)) + (match_dup 3)) + (const_int 1))))] + "TARGET_SSSE3" +{ + operands[3] = CONST1_RTX(V4HImode); + ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands); +}) + (define_insn "*ssse3_pmulhrswv4hi3" [(set (match_operand:V4HI 0 "register_operand" "=y") (truncate:V4HI |