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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2011-02-03 00:41:16 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2011-02-03 00:41:16 +0000 |
| commit | 28fc3eee79d92a367a179ef4e7fa5d8ed134fe61 (patch) | |
| tree | 0156ac6b1c884f4d2ea42bdddbf6074b0719130e | |
| parent | 1fb4a78837a7c1e5b81a319784180914462684d2 (diff) | |
| download | gcc-28fc3eee79d92a367a179ef4e7fa5d8ed134fe61.zip gcc-28fc3eee79d92a367a179ef4e7fa5d8ed134fe61.tar.gz gcc-28fc3eee79d92a367a179ef4e7fa5d8ed134fe61.tar.bz2 | |
Fix PR target/47580
From-SVN: r169776
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 19 |
2 files changed, 20 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4534352..1bcd269 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2011-02-01 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/47580 + * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use + gpc_reg_operand instead of vsx_register_operand to match rs6000.md + generator functions. + (vsx_floatuns<VSi><mode>2): Ditto. + (vsx_fix_trunc<mode><VSi>2): Ditto. + (vsx_fixuns_trunc<mode><VSi>2): Ditto. + 2011-02-02 Joseph Myers <joseph@codesourcery.com> * config/i386/djgpp.opt (posix): New Driver option. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e241e26..5b3040c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1,5 +1,5 @@ ;; VSX patterns. -;; Copyright (C) 2009, 2010 +;; Copyright (C) 2009, 2010, 2011 ;; Free Software Foundation, Inc. ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> @@ -695,33 +695,34 @@ ;; the fprs because we don't want to add the altivec registers to movdi/movsi. ;; For the unsigned tests, there isn't a generic double -> unsigned conversion ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. +;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. (define_insn "vsx_float<VSi><mode>2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))] + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + (float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvsx<VSc><VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_floatuns<VSi><mode>2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unsigned_float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))] + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + (unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvux<VSc><VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_fix_trunc<mode><VSi>2" - [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>") - (fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") + (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>sx<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_fixuns_trunc<mode><VSi>2" - [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>") - (unsigned_fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") + (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>ux<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") |