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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2020-10-08 15:44:46 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2020-10-13 14:41:27 +0100 |
| commit | 25095d1ef8dd24c646fd337a607fb94a06e73f6c (patch) | |
| tree | 94965979ecca1c84a3e8796eded26a60bd15781e | |
| parent | 7287cf184e3aef6e55da717c7acc86cf02500e79 (diff) | |
| download | gcc-25095d1ef8dd24c646fd337a607fb94a06e73f6c.zip gcc-25095d1ef8dd24c646fd337a607fb94a06e73f6c.tar.gz gcc-25095d1ef8dd24c646fd337a607fb94a06e73f6c.tar.bz2 | |
AArch64: Add Neoverse N2 tuning model
This patch adds a tuning structure for Neoverse N2 to allow for further
tuning.
For now it's just a deduplication of the Neoverse N1 struct that it was
reusing but with the SVE width set to 128.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
* config/aarch64/aarch64.c (neoversen2_tunings): Define.
* config/aarch64/aarch64-cores.def (neoverse-n2): Use it.
| -rw-r--r-- | gcc/config/aarch64/aarch64-cores.def | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 26 |
2 files changed, 27 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index b2e1932..3aa13f6 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -143,7 +143,7 @@ AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) /* Armv8.5-A Architecture Processors. */ -AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_5A, AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG, neoversen1, 0x41, 0xd49, -1) +AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_5A, AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG, neoversen2, 0x41, 0xd49, -1) /* ARMv8-A big.LITTLE implementations. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3cf20ea..a8cc545 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1362,6 +1362,32 @@ static const struct tune_params neoversev1_tunings = &generic_prefetch_tune }; +static const struct tune_params neoversen2_tunings = +{ + &cortexa57_extra_costs, + &generic_addrcost_table, + &generic_regmove_cost, + &cortexa57_vector_cost, + &generic_branch_cost, + &generic_approx_modes, + SVE_128, /* sve_width */ + 4, /* memmov_cost */ + 3, /* issue_rate */ + (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops */ + "32:16", /* function_align. */ + "4", /* jump_align. */ + "32:16", /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 2, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune +}; + static const struct tune_params a64fx_tunings = { &generic_extra_costs, |