h8300.md (movqi_internal): Remove useless alternative(s).

        * h8300.md (movqi_internal): Remove useless alternative(s).  Fix
        lengths and simplify by reordering remaining alternatives.
        (movestrictqi, movhi_internal, movstricthi): Likewise.
        (movsi_h8300h, movsf_h8300h): Likewise.

From-SVN: r11655

1 files changed, 23 insertions, 33 deletions

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 509c960..6dd9f7d 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -32,6 +32,9 @@
 ;; ??? If we can remove the operand type on all the insns, do it.
 ;; ??? Otherwise, try to have the operand type on all the insns.
 
+;; Some move patterns have conditions which check that one operand
+;; is a register.  Shouldn't all of them have such a condition?
+
 (define_attr "type" "branch,return,call,arith,move,float,multi"
   (const_string "arith"))
 
@@ -92,10 +95,9 @@
    (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
    (set_attr "cc" "set")])
 
-;; ??? Use of the `c' constraint doesn't seem right.
 (define_insn "movqi_internal"
-  [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<,r")
-	(match_operand:QI 1 "general_operand_src" "I,r>,io,r,r,c"))]
+  [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,o")
+	(match_operand:QI 1 "general_operand_src" "I,r>,r,io,r"))]
   "register_operand (operands[0],QImode)
    || register_operand (operands[1], QImode)"
   "@
@@ -103,16 +105,13 @@
    mov.b	%X1,%X0
    mov.b	%X1,%X0
    mov.b	%X1,%X0
-   mov.b	%X1,%X0
-   xor		%X0,%X0\;bst	#0,%X0"
+   mov.b	%X1,%X0"
   [(set_attr "type" "move")
    (set_attr_alternative "length"
-     [(const_int 2) (const_int 2)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
+     [(const_int 2) (const_int 2) (const_int 2)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))
-      (const_int 4)])
-   (set_attr "cc" "set_zn_c0,set,set,set,set,clobber")])
+      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
+   (set_attr "cc" "set_zn_c0,set,set,set,set")])
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand_dst" "")
@@ -129,22 +128,18 @@
 }")
 
 (define_insn "movstrictqi"
-  [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<"))
-			 (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))]
+  [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r"))
+			 (match_operand:QI 1 "general_operand_src" "I,r,io"))]
   ""
   "@
    sub.b	%X0,%X0
    mov.b	%X1,%X0
-   mov.b	%X1,%X0
-   mov.b	%X1,%X0
    mov.b	%X1,%X0"
   [(set_attr "type" "move")
    (set_attr_alternative "length"
      [(const_int 2) (const_int 2)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
-   (set_attr "cc" "set_zn_c0,set,set,set,set")])
+      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
+   (set_attr "cc" "set_zn_c0,set,set")])
    
 ;; movhi
 
@@ -164,8 +159,8 @@
    (set_attr "cc" "set")])
 
 (define_insn "movhi_internal"
-  [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<")
-	(match_operand:HI 1 "general_operand_src" "I,ra>,ion,ra,ra"))]
+  [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,<,ra,o")
+	(match_operand:HI 1 "general_operand_src" "I,ra>,ra,ion,ra"))]
   ""
   "@
    sub.w	%T0,%T0
@@ -175,10 +170,9 @@
    mov.w	%T1,%T0"
   [(set_attr "type" "move")
    (set_attr_alternative "length"
-     [(const_int 2) (const_int 2)
+     [(const_int 2) (const_int 2) (const_int 2)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
+      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
    (set_attr "cc" "set_zn_c0,set,set,set,set")])
 
 (define_expand "movhi"
@@ -196,22 +190,18 @@
 }")
 
 (define_insn "movstricthi"
-  [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<"))
-			 (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))]
+  [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r"))
+			 (match_operand:HI 1 "general_operand_src" "I,r,io"))]
   ""
   "@
    sub.w	%T0,%T0
    mov.w	%T1,%T0
-   mov.w	%T1,%T0
-   mov.w	%T1,%T0
    mov.w	%T1,%T0"
   [(set_attr "type" "move")
    (set_attr_alternative "length"
      [(const_int 2) (const_int 2)
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
-      (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
-   (set_attr "cc" "set_zn_c0,set,set,set,set")])
+      (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
+   (set_attr "cc" "set_zn_c0,set,set")])
 
 ;; movsi
 
@@ -391,7 +381,7 @@
    mov.l	%S1,%S0
    mov.l	%S1,%S0"
   [(set_attr "type" "move")
-   (set_attr "length" "2,2,8,8,4,4")
+   (set_attr "length" "2,2,10,10,4,4")
    (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
 
 (define_insn "movsf_h8300h"
@@ -408,7 +398,7 @@
    mov.l	%S1,%S0
    mov.l	%S1,%S0"
   [(set_attr "type" "move")
-   (set_attr "length" "2,2,8,8,4,4")
+   (set_attr "length" "2,2,10,10,4,4")
    (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
 
 ;; ----------------------------------------------------------------------