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author | Eric Botcazou <ebotcazou@adacore.com> | 2017-02-23 23:04:00 +0000 |
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committer | Eric Botcazou <ebotcazou@gcc.gnu.org> | 2017-02-23 23:04:00 +0000 |
commit | 195610aaa05ba8ee8f3ec4bd5df3877610a5daf3 (patch) | |
tree | 970ff0395406b5420ea5ca9c66fa5c374aeed8e6 | |
parent | ada61c3d4774b98d42b53e99836abd695969fbc6 (diff) | |
download | gcc-195610aaa05ba8ee8f3ec4bd5df3877610a5daf3.zip gcc-195610aaa05ba8ee8f3ec4bd5df3877610a5daf3.tar.gz gcc-195610aaa05ba8ee8f3ec4bd5df3877610a5daf3.tar.bz2 |
visium.md (type): Add trap.
* config/visium/visium.md (type): Add trap.
(b): New mode attribute.
(*btst): Rename into...
(*btst<mode>): ...this and adjust.
(*cbranchsi4_btst_insn): Rename into...
(*cbranch<mode>4_btst_insn): ...this and adjust.
(trap): New define_insn.
From-SVN: r245691
-rw-r--r-- | gcc/ChangeLog | 10 | ||||
-rw-r--r-- | gcc/config/visium/visium.md | 32 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/visium/bit_test.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/visium/block_move.c | 2 |
5 files changed, 41 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ffb5e25..68cd88f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-02-23 Eric Botcazou <ebotcazou@adacore.com> + + * config/visium/visium.md (type): Add trap. + (b): New mode attribute. + (*btst): Rename into... + (*btst<mode>): ...this and adjust. + (*cbranchsi4_btst_insn): Rename into... + (*cbranch<mode>4_btst_insn): ...this and adjust. + (trap): New define_insn. + 2017-02-23 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/79389 diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md index 87fa9b6..501e874 100644 --- a/gcc/config/visium/visium.md +++ b/gcc/config/visium/visium.md @@ -137,9 +137,10 @@ ;nop No operation. ;multi Multiple instructions which split. ;asm User asm instructions. +;trap Trap instructions. (define_attr "type" -"imm_reg,mem_reg,eam_reg,fp_reg,reg_mem,reg_eam,reg_fp,arith,arith2,logic,abs_branch,branch,bmi,call,ret,rfi,dsi,cmp,div,divd,mul,shiftdi,fdiv,fsqrt,ftoi,itof,fmove,fcmp,fp,nop,multi,asm" (const_string "logic")) +"imm_reg,mem_reg,eam_reg,fp_reg,reg_mem,reg_eam,reg_fp,arith,arith2,logic,abs_branch,branch,bmi,call,ret,rfi,dsi,cmp,div,divd,mul,shiftdi,fdiv,fsqrt,ftoi,itof,fmove,fcmp,fp,nop,multi,asm,trap" (const_string "logic")) ; Those insns that occupy 4 bytes. (define_attr "single_insn" "no,yes" @@ -205,6 +206,7 @@ (define_mode_iterator QHI [QI HI]) (define_mode_iterator I [QI HI SI]) +(define_mode_attr b [(QI "8") (HI "16") (SI "32")]) (define_mode_attr s [(QI ".b") (HI ".w") (SI ".l")]) ; This code iterator allows signed and unsigned widening multiplications @@ -1986,15 +1988,15 @@ ; BITS_BIG_ENDIAN is defined to 1 so operand #1 counts from the MSB. -(define_insn "*btst" +(define_insn "*btst<mode>" [(set (reg:CCC R_FLAGS) - (compare:CCC (zero_extract:SI - (match_operand:SI 0 "register_operand" "r") + (compare:CCC (zero_extract:I + (match_operand:I 0 "register_operand" "r") (const_int 1) (match_operand:QI 1 "const_shift_operand" "K")) (const_int 0)))] "reload_completed" - "lsr.l r0,%0,32-%1" + "lsr<s> r0,%0,<b>-%1" [(set_attr "type" "logic")]) ;; @@ -2373,11 +2375,11 @@ } [(set_attr "type" "cmp")]) -(define_insn_and_split "*cbranchsi4_btst_insn" +(define_insn_and_split "*cbranch<mode>4_btst_insn" [(set (pc) (if_then_else (match_operator 0 "visium_equality_comparison_operator" - [(zero_extract:SI - (match_operand:SI 1 "register_operand" "r") + [(zero_extract:I + (match_operand:I 1 "register_operand" "r") (const_int 1) (match_operand:QI 2 "const_shift_operand" "K")) (const_int 0)]) @@ -2513,6 +2515,20 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; +;; trap instructions +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; + +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "stop 0,r0" + [(set_attr "type" "trap")]) + +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; ;; Subprogram call instructions ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0bd9f06..96a0234 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-02-23 Eric Botcazou <ebotcazou@adacore.com> + + * gcc.target/visium/bit_test.c: Accept any lsr form. + * gcc.target/visium/block_move.c: Tweak. + 2017-02-23 Dominik Vogt <vogt@linux.vnet.ibm.com> PR 68749 diff --git a/gcc/testsuite/gcc.target/visium/bit_test.c b/gcc/testsuite/gcc.target/visium/bit_test.c index 2de9208f..8fbb87e 100644 --- a/gcc/testsuite/gcc.target/visium/bit_test.c +++ b/gcc/testsuite/gcc.target/visium/bit_test.c @@ -27,5 +27,5 @@ void foo4 (unsigned char c) bar (); } -/* { dg-final { scan-assembler-times "lsr.l" 2 } } */ +/* { dg-final { scan-assembler-times "lsr" 2 } } */ /* { dg-final { scan-assembler-times "cmp" 2 } } */ diff --git a/gcc/testsuite/gcc.target/visium/block_move.c b/gcc/testsuite/gcc.target/visium/block_move.c index d85c135..f66c261 100644 --- a/gcc/testsuite/gcc.target/visium/block_move.c +++ b/gcc/testsuite/gcc.target/visium/block_move.c @@ -11,7 +11,7 @@ void foo (void) int dst[LEN], src[LEN]; unsigned int i; - __builtin_memset (src, 0, LEN * sizeof (int)); + __builtin_memset (src, 1, LEN * sizeof (int)); __builtin_memcpy (dst, src, LEN * sizeof (int)); if (__builtin_memcmp (dst, src, LEN * sizeof (int)) != 0) abort (); |