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| author | David Edelsohn <dje.gcc@gmail.com> | 2013-04-16 17:49:14 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2013-04-16 13:49:14 -0400 |
| commit | 18a6701e5b0d7eecd64751e17cfae5069a12745d (patch) | |
| tree | 15baa72491c10de3e7d2faf41ce08e31334ed20c | |
| parent | 07c37b2fba70f106809feb253be848d4232252bb (diff) | |
| download | gcc-18a6701e5b0d7eecd64751e17cfae5069a12745d.zip gcc-18a6701e5b0d7eecd64751e17cfae5069a12745d.tar.gz gcc-18a6701e5b0d7eecd64751e17cfae5069a12745d.tar.bz2 | |
re PR target/56948 (PPC V2DI ICE when loading zero into GPRs)
PR target/56948
* config/rs6000/vsx.md (vsx_mov<mode>): Add j->r alternative.
(vsx_movti_64bit): Change j->wa to O->wa. Add n->r alternative.
(vsx_movti_32bit): Change j->wa to O->wa.
From-SVN: r198007
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 24 |
2 files changed, 20 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 343947b..7cb659c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-04-16 David Edelsohn <dje.gcc@gmail.com> + + PR target/56948 + * config/rs6000/vsx.md (vsx_mov<mode>): Add j->r alternative. + (vsx_movti_64bit): Change j->wa to O->wa. Add n->r alternative. + (vsx_movti_32bit): Change j->wa to O->wa. + 2013-04-16 Richard Biener <rguenther@suse.de> PR rtl-optimization/56921 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 042bb5c..4adf6e5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -207,8 +207,8 @@ ;; VSX moves (define_insn "*vsx_mov<mode>" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,v,wZ,v") - (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,W,v,wZ"))] + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,*r,v,wZ,v") + (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))] "VECTOR_MEM_VSX_P (<MODE>mode) && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -238,23 +238,24 @@ case 6: case 7: case 8: + case 11: return "#"; case 9: case 10: return "xxlxor %x0,%x0,%x0"; - case 11: + case 12: return output_vec_const_move (operands); - case 12: + case 13: gcc_assert (MEM_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) != PRE_INC && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY); return "stvx %1,%y0"; - case 13: + case 14: gcc_assert (MEM_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) != PRE_INC && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC @@ -265,14 +266,14 @@ gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,vecstore,vecload")]) + [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,*,vecstore,vecload")]) ;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal ;; use of TImode is for unions. However for plain data movement, slightly ;; favor the vector loads (define_insn "*vsx_movti_64bit" - [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,?Y,?r,?r") - (match_operand:TI 1 "input_operand" "wa, Z,wa, j,W,wZ, v, r, Y, r"))] + [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,?Y,?r,?r,?r") + (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v, r, Y, r, n"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode))" @@ -303,18 +304,19 @@ case 7: case 8: case 9: + case 10: return "#"; default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,*,*,*") - (set_attr "length" " 4, 4, 4, 4, 8, 4, 4,8,8,8")]) + [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,*,*,*,*") + (set_attr "length" " 4, 4, 4, 4, 8, 4, 4,8,8,8,8")]) (define_insn "*vsx_movti_32bit" [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r") - (match_operand:TI 1 "input_operand" "wa, Z,wa, j,W,wZ, v,r,r, Q, Y, r,n"))] + (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))] "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode))" |