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| author | Sudi Das <sudi.das@arm.com> | 2020-09-18 16:31:12 +0100 |
|---|---|---|
| committer | Omar Tahir <omar.tahir@arm.com> | 2020-09-18 17:05:05 +0100 |
| commit | 04dc198ce5508b2329c83cda7c0cd9bce4ed83bb (patch) | |
| tree | 7bbf3f78f23ad2fec798915b6e18b5b5d2a5ae1f | |
| parent | 778f19ff953792702c0a7e1fde00214709d9317e (diff) | |
| download | gcc-04dc198ce5508b2329c83cda7c0cd9bce4ed83bb.zip gcc-04dc198ce5508b2329c83cda7c0cd9bce4ed83bb.tar.gz gcc-04dc198ce5508b2329c83cda7c0cd9bce4ed83bb.tar.bz2 | |
[PATCH 4/5][Arm] New pattern for CSNEG instructions
This patch adds a new pattern, *thumb2_csneg, for generating CSNEG
instructions. It also restricts *if_neg_move and *thumb2_negscc to only match
if !TARGET_COND_ARITH which prevents undesirable matches during ifcvt.
gcc/ChangeLog:
* config/arm/thumb2.md (*thumb2_csneg): New.
(*thumb2_negscc): Don't match if TARGET_COND_ARITH.
* config/arm/arm.md (*if_neg_move): Don't match if TARGET_COND_ARITH.
gcc/testsuite/ChangeLog:
* gcc.target/arm/csneg.c: New test.
Co-authored-by: Omar Tahir <omar.tahir@arm.com>
| -rw-r--r-- | gcc/config/arm/arm.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/csneg.c | 33 |
3 files changed, 49 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index dd13c77..bffdb0b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11213,7 +11213,7 @@ [(match_operand 3 "cc_register" "") (const_int 0)]) (neg:SI (match_operand:SI 2 "s_register_operand" "l,r")) (match_operand:SI 1 "s_register_operand" "0,0")))] - "TARGET_32BIT" + "TARGET_32BIT && !TARGET_COND_ARITH" "#" "&& reload_completed" [(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)]) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 0ff5a53..2a8fdf2 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -881,7 +881,7 @@ [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB2" + "TARGET_THUMB2 && !TARGET_COND_ARITH" "#" "&& reload_completed" [(const_int 0)] @@ -971,6 +971,20 @@ (set_attr "predicable" "no")] ) +(define_insn "*thumb2_csneg" + [(set (match_operand:SI 0 "arm_general_register_operand" "=r, r") + (if_then_else:SI + (match_operand 1 "arm_comparison_operation" "") + (neg:SI (match_operand:SI 2 "arm_general_register_operand" "r, r")) + (match_operand:SI 3 "reg_or_zero_operand" "r, Pz")))] + "TARGET_COND_ARITH" + "@ + csneg\\t%0, %3, %2, %D1 + csneg\\t%0, zr, %2, %D1" + [(set_attr "type" "csel") + (set_attr "predicable" "no")] +) + (define_insn "*thumb2_movcond" [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts") (if_then_else:SI diff --git a/gcc/testsuite/gcc.target/arm/csneg.c b/gcc/testsuite/gcc.target/arm/csneg.c new file mode 100644 index 0000000..e486062 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/csneg.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */ +/* { dg-options "-O2 -march=armv8.1-m.main" } */ + +int +test_csneg32_condasn1(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ + w4 = (w0 == w1) ? -w2 : w3; + return w4; +} + +int +test_csneg32_condasn2(int w0, int w1, int w2, int w3) +{ + int w4; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*eq" } } */ + w4 = (w0 == w1) ? w3 : -w2; + return w4; +} + +unsigned long long +test_csneg_uxtw (unsigned int a, unsigned int b, unsigned int c) +{ + unsigned int val; + + /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ + val = a ? b : -c; + return val; +} |