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authorChristophe Lyon <christophe.lyon@arm.com>2023-02-21 13:33:28 +0000
committerChristophe Lyon <christophe.lyon@arm.com>2023-05-11 10:25:11 +0200
commitfa2c9dbb6ea474bcfc02bd6d92903397129b4e57 (patch)
tree1298e3cee8cec1ae04fcdc764f2792b07543be9e
parent7e3c2d23cfdc479d5022fa4de56841bd032e915b (diff)
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arm: [MVE intrinsics] factorize vaddlvq
Factorize vaddlvq builtins so that they use parameterized names. 2022-10-25 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vaddlv. * config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vaddlvq_p_<supf>v4si): Rename into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
-rw-r--r--gcc/config/arm/iterators.md2
-rw-r--r--gcc/config/arm/mve.md8
2 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 00123c0..84dd972 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -759,6 +759,8 @@
(VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd")
(VABSQ_M_F "vabs")
(VABSQ_M_S "vabs")
+ (VADDLVQ_P_S "vaddlv") (VADDLVQ_P_U "vaddlv")
+ (VADDLVQ_S "vaddlv") (VADDLVQ_U "vaddlv")
(VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd")
(VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd")
(VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 1ccbce3..c5373fe 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -500,14 +500,14 @@
;;
;; [vaddlvq_s vaddlvq_u])
;;
-(define_insn "mve_vaddlvq_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
VADDLVQ))
]
"TARGET_HAVE_MVE"
- "vaddlv.<supf>32\t%Q0, %R0, %q1"
+ "<mve_insn>.<supf>32\t%Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
@@ -666,7 +666,7 @@
;;
;; [vaddlvq_p_s])
;;
-(define_insn "mve_vaddlvq_p_<supf>v4si"
+(define_insn "@mve_<mve_insn>q_p_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
@@ -674,7 +674,7 @@
VADDLVQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vaddlvt.<supf>32\t%Q0, %R0, %q1"
+ "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1"
[(set_attr "type" "mve_move")
(set_attr "length""8")])