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| author | Carl Love <cel@us.ibm.com> | 2018-06-25 15:43:34 +0000 |
|---|---|---|
| committer | Carl Love <carll@gcc.gnu.org> | 2018-06-25 15:43:34 +0000 |
| commit | f74fc01dcdf9d84975025826d1ab468b9e90674a (patch) | |
| tree | 00977656c79bd51790e3efeb507ad0d5daf01b31 | |
| parent | 2817a2b6b528805a961909d45db96c0e1d14e4f3 (diff) | |
| download | gcc-f74fc01dcdf9d84975025826d1ab468b9e90674a.zip gcc-f74fc01dcdf9d84975025826d1ab468b9e90674a.tar.gz gcc-f74fc01dcdf9d84975025826d1ab468b9e90674a.tar.bz2 | |
vsx.md: Change word selector to prefered location.
gcc/ChangeLog:
2018-06-25 Carl Love <cel@us.ibm.com>
* config/rs6000/vsx.md: Change word selector to prefered location.
Signed-off-by: Carl Love <cel@us.ibm.com>
---
gcc/config/rs6000/vsx.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a528ef2e8..6e7a4277f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3934,7 +3934,7 @@
operands[5] = gen_rtx_REG (V4SFmode, tmp_regno);
operands[6] = gen_rtx_REG (V4SImode, tmp_regno);
- operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 1 : 2);
+ operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 0 : 3);
operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
}
[(set_attr "type" "vecperm")
--
2.17.1
From-SVN: r262020
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84b8b64..754b5f1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2018-06-25 Carl Love <cel@us.ibm.com> + + * config/rs6000/vsx.md: Change word selector to prefered location. + 2018-06-25 Richard Biener <rguenther@suse.de> PR tree-optimization/86304 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6fe18c3..432aa1e 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3934,7 +3934,7 @@ operands[5] = gen_rtx_REG (V4SFmode, tmp_regno); operands[6] = gen_rtx_REG (V4SImode, tmp_regno); - operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 1 : 2); + operands[7] = GEN_INT (BYTES_BIG_ENDIAN ? 0 : 3); operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0])); } [(set_attr "type" "vecperm") |