Improvements to aarch64 target hook

2 files changed, 117 insertions, 96 deletions

diff --git a/gcc/config/aarch64/aarch64-rust.c b/gcc/config/aarch64/aarch64-rust.c
index c1a4e73..67d1c92 100644
--- a/gcc/config/aarch64/aarch64-rust.c
+++ b/gcc/config/aarch64/aarch64-rust.c
@@ -19,108 +19,128 @@ along with GCC; see the file COPYING3.  If not see
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
+#include "tm_p.h"
 #include "rust/rust-target.h"
 #include "rust/rust-target-def.h"
 
 /* Implement TARGET_RUST_CPU_INFO for AArch64 targets.  */
 
-void
-aarch64_rust_target_cpu_info (void)
-{
-  rust_add_target_info ("target_arch", "aarch64");
+void aarch64_rust_target_cpu_info(void) {
+    rust_add_target_info("target_arch", "aarch64");
 
-  // TODO: properly change at some point instead of macro def
-#ifndef isa_flag
-# define isa_flag aarch64_isa_flags
-# define isa_flag2 aarch64_isa_flags2
-//# define fpmath aarch64_fpmath
-#else
-# error "isa_flag and isa_flag2 already defined in aarch64-rust.c - weird things might happen"
-#endif
-  // FIXME: almost feature-complete with rustc, missing "ras" feature (which may not be in gcc)
+    // TODO: almost feature-complete with rustc - missing "ras" feature (which is not in gcc)
 
-  if (TARGET_SIMD) 
-    rust_add_target_info ("target_feature", "neon");
-  /* appears to be what is referred to what seems to be referred to
-  as "fp-armv8" in rust, at least in target def, based on closeness of it in aarch64.h to TARGET_SIMD */
-  if (TARGET_FLOAT) {
-    rust_add_target_info ("target_feature", "fp-armv8");
-    // seems to be translated to "fp", but can't tell if "fp-armv8" exists too
-    rust_add_target_info ("target_feature", "fp");
-  }
-  /*if (TARGET_CYCLONE) - need to find this feature (if it exists)
-    rust_add_target_info ("target_feature", "cyclone");*/  
-  /* appears to be what is referred to what seems to be referred to
-  as "strict-align" in rust, at least in target def according to notes in aarch64.h 
-  otherwise strict-align could be STRICT_ALIGNMENT (which evaluates to same thing unless macro redefed) */
-  if (TARGET_STRICT_ALIGN) 
-    rust_add_target_info ("target_feature", "strict-align");
-  // below all derived from llvm code - i'm pretty sure they correspond
-  if (TARGET_CRC32) 
-    rust_add_target_info ("target_feature", "crc");
-  if (TARGET_CRYPTO) 
-    rust_add_target_info ("target_feature", "crypto");
-  if (TARGET_DOTPROD) 
-    rust_add_target_info ("target_feature", "dotprod");
-  if (TARGET_F16FML) 
-    rust_add_target_info ("target_feature", "fp16fml");
-  if (TARGET_FP_F16INST) {
-    rust_add_target_info ("target_feature", "fullfp16");
-    // seems to be translated to "fp16", but not sure, so keep that here too
-    rust_add_target_info ("target_feature", "fp16");
-  }
-  // TODO: some feature relating to profiling with feature name "spe" - can't find atm
-  if (TARGET_LSE)
-    rust_add_target_info ("target_feature", "lse");
-  // hope this is the right thing - llvm calls it "rdm" - TODO ensure that it is
-  if (AARCH64_ISA_RDMA)
-    rust_add_target_info ("target_feature", "rdm");
-  if (TARGET_SVE)
-    rust_add_target_info ("target_feature", "sve");
-  if (TARGET_SVE2)
-    rust_add_target_info ("target_feature", "sve2");
-  if (isa_flag & AARCH64_FL_SVE2_AES)
-    rust_add_target_info ("target_feature", "sve2-aes");
-  if (isa_flag & AARCH64_FL_SVE2_SM4)
-    rust_add_target_info ("target_feature", "sve2-sm4");
-  if (isa_flag & AARCH64_FL_SVE2_SHA3)
-    rust_add_target_info ("target_feature", "sve2-sha3");
-  if (isa_flag & AARCH64_FL_SVE2_BITPERM)
-    rust_add_target_info ("target_feature", "sve2-bitperm");
-  // TODO: assuming that this is the correct RCPC and that the AARCH64_FL_RCPC8_4 is not
-  if (isa_flag & AARCH64_FL_RCPC)
-    rust_add_target_info ("target_feature", "rcpc");
-  // TODO: find below target features if they exist
-  /*if (TARGET_ZCM)
-    rust_add_target_info ("target_feature", "zcm");*/
-  /*if (TARGET_ZCZ)
-    rust_add_target_info ("target_feature", "zcz");*/
-  // some possible target features: "thumb-mode"
-  if (TARGET_SM4)
-    rust_add_target_info ("target_feature", "sm4");
-  if (TARGET_SHA3)
-    rust_add_target_info ("target_feature", "sha3");
-  if (TARGET_SHA2)
-    rust_add_target_info ("target_feature", "sha2");
-  if (TARGET_AES)
-    rust_add_target_info ("target_feature", "aes");
-  if (TARGET_TME)
-    rust_add_target_info ("target_feature", "tme");
-  if (TARGET_MEMTAG)
-    rust_add_target_info ("target_feature", "mte");
+    // features from rustc
+    if (TARGET_FLOAT) {
+        rust_add_target_info("target_feature", "fp-armv8");
+        rust_add_target_info("target_feature", "fp");
+    }
+    if (TARGET_SIMD)
+        rust_add_target_info("target_feature", "neon");
+    if (TARGET_SVE)
+        rust_add_target_info("target_feature", "sve");
+    if (TARGET_CRC32)
+        rust_add_target_info("target_feature", "crc");
+    if (TARGET_CRYPTO)
+        rust_add_target_info("target_feature", "crypto");
+    if (TARGET_LSE)
+        rust_add_target_info("target_feature", "lse");
+    if (AARCH64_ISA_RDMA)
+        rust_add_target_info("target_feature", "rdm");
+    if (TARGET_FP_F16INST) {
+        rust_add_target_info("target_feature", "fullfp16");
+        rust_add_target_info("target_feature", "fp16");
+    }
+    if (aarch64_isa_flags & AARCH64_FL_RCPC)
+        rust_add_target_info("target_feature", "rcpc");
+    if (TARGET_DOTPROD)
+        rust_add_target_info("target_feature", "dotprod");
+    if (AARCH64_ISA_V8_1)
+        rust_add_target_info("target_feature", "v8.1a");
+    if (AARCH64_ISA_V8_2)
+        rust_add_target_info("target_feature", "v8.2a");
+    if (AARCH64_ISA_V8_3)
+        rust_add_target_info("target_feature", "v8.3a");
 
-  if (AARCH64_ISA_V8_1)
-    rust_add_target_info ("target_feature", "v8.1a");
-  if (AARCH64_ISA_V8_2)
-    rust_add_target_info ("target_feature", "v8.2a");
-  if (AARCH64_ISA_V8_3)
-    rust_add_target_info ("target_feature", "v8.3a");
-  if (AARCH64_ISA_V8_4)
-    rust_add_target_info ("target_feature", "v8.4a");
-  if (AARCH64_ISA_V8_5)
-    rust_add_target_info ("target_feature", "v8.5a");
-    
-#undef isa_flag
-#undef isa_flag2
-//#undef fpmath
+    // llvm-derived features
+    if (TARGET_SM4)
+        rust_add_target_info("target_feature", "sm4");
+    if (TARGET_SHA2)
+        rust_add_target_info("target_feature", "sha2");
+    if (TARGET_SHA3)
+        rust_add_target_info("target_feature", "sha3");
+    if (TARGET_AES)
+        rust_add_target_info("target_feature", "aes");
+    if (TARGET_F16FML)
+        rust_add_target_info("target_feature", "fp16fml");
+    if (aarch64_isa_flags & AARCH64_FL_PROFILE)
+        rust_add_target_info("target_feature", "spe");
+    if (TARGET_SVE2)
+        rust_add_target_info("target_feature", "sve2");
+    if (aarch64_isa_flags & AARCH64_FL_SVE2_AES)
+        rust_add_target_info("target_feature", "sve2-aes");
+    if (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
+        rust_add_target_info("target_feature", "sve2-sm4");
+    if (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
+        rust_add_target_info("target_feature", "sve2-sha3");
+    if (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
+        rust_add_target_info("target_feature", "sve2-bitperm");
+    if (TARGET_STRICT_ALIGN)
+        rust_add_target_info("target_feature", "strict-align");
+    if (flag_mrecip_low_precision_sqrt)
+        rust_add_target_info("target_feature", "use-reciprocal-square-root");
+    if (TARGET_JSCVT)
+        rust_add_target_info("target_feature", "jsconv");
+    if (TARGET_COMPLEX)
+        rust_add_target_info("target_feature", "complxnum");
+    if (AARCH64_ISA_RCPC8_4)
+        rust_add_target_info("target_feature", "rcpc-immo");
+    if (TARGET_FRINT)
+        rust_add_target_info("target_feature", "fptoint");
+    if (aarch64_isa_flags & AARCH64_FL_SB)
+        rust_add_target_info("target_feature", "sb");
+    if (aarch64_isa_flags & AARCH64_FL_SSBS)
+        rust_add_target_info("target_feature", "ssbs");
+    if (aarch64_isa_flags & AARCH64_FL_PREDRES)
+        rust_add_target_info("target_feature", "predres");
+    if (aarch64_enable_bti)
+        rust_add_target_info("target_feature", "bti");
+    if (AARCH64_ISA_RNG)
+        rust_add_target_info("target_feature", "rand");
+    if (TARGET_MEMTAG)
+        rust_add_target_info("target_feature", "mte");
+    if (TARGET_TME)
+        rust_add_target_info("target_feature", "tme");
+    if (AARCH64_ISA_BF16)
+        rust_add_target_info("target_feature", "bf16");
+    if (AARCH64_ISA_I8MM)
+        rust_add_target_info("target_feature", "i8mm");
+    if (AARCH64_ISA_F32MM)
+        rust_add_target_info("target_feature", "f32mm");
+    if (AARCH64_ISA_F64MM)
+        rust_add_target_info("target_feature", "f64mm");
+    if (AARCH64_ISA_V8_4)
+        rust_add_target_info("target_feature", "v8.4a");
+    if (AARCH64_ISA_V8_5)
+        rust_add_target_info("target_feature", "v8.5a");
+    if (AARCH64_ISA_V8_6)
+        rust_add_target_info("target_feature", "v8.6a");
+
+    /* TODO: find features for pan (Privileged Access-Never), lor (Limited Ordering Regions),
+     * vh (Virtual Host), perfmon, pan-rwv (PAN s1e1R and s1e1W variants),
+     * uaops (UAO PState), ccpp (Cache Clean to Point of Persistence), zcm (zero-cycle register move),
+     * zcz-gp (zero-cycle zeroing for generic regs), zcz-fp (zero-cycle zeroing for FP regs), zcz
+     * (both), zcz-fp-workaround, reserve specific registers, make specific registers callee saved,
+     * use-aa (alias analysis), balance-fp-ops, predictable-select-expensive, custom-cheap-as-move,
+     * exynos-cheap-as-move, use-postra-scheduler, slow-misaligned-128store, slow-paired-128,
+     * slow-strqro-store, alternate-sextload-cvt-f32-pattern, arith-bcc-fusion, arith-cbz-fusion,
+     * fuse-address, fuse-aes, fuse-arith-logic, fuse-csel, fuse-crypto-eor, fuse-literals,
+     * disable-latency-sched-heuristic, force-32bit-jump-tables, pa
+     * (Pointer Authentication), ccidx (extend CCSIDR number of sets),
+     * nv (Nested Virtualisation), rasv8_4, mpam (Memory system Partitioning and Monitoring),
+     * dit (Data Independent Timing), tracev8.4, am (Activity Monitors), amvs (Activity Monitors
+     * Virtualisation), sel2 (Secure Exception Level 2), pmu, tlb-rmi (TLB Range and Maintenance), fmi
+     * (Flag Manipulation), no-neg-immediates, lsl-fast, aggressive-fma,
+     * altnzcv, specrestrict, ccdp, trbe, ete, tagged-globals, fgt, ecv, maybe cpus */
+    // gcc supports pointer authentication, but i can only find builtins and no switch for it
 }
diff --git a/gcc/config/i386/i386-rust.c b/gcc/config/i386/i386-rust.c
index 63f0fef..49f8d37 100644
--- a/gcc/config/i386/i386-rust.c
+++ b/gcc/config/i386/i386-rust.c
@@ -19,6 +19,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
+#include "tm_p.h"
 #include "rust/rust-target.h"
 #include "rust/rust-target-def.h"