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| author | Maciej W. Rozycki <macro@embecosm.com> | 2023-11-22 01:18:27 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@embecosm.com> | 2023-11-22 01:18:27 +0000 |
| commit | eeb112542f9a93974ee17d582ba649c50af95c86 (patch) | |
| tree | c58b370e12df5e8f89de60ccdacf50c8c57bd75b | |
| parent | c47fb7d09ea7b152f48129fb73af1bb24d65fcc3 (diff) | |
| download | gcc-eeb112542f9a93974ee17d582ba649c50af95c86.zip gcc-eeb112542f9a93974ee17d582ba649c50af95c86.tar.gz gcc-eeb112542f9a93974ee17d582ba649c50af95c86.tar.bz2 | |
RISC-V: Also accept constants for T-Head cond-move comparison operands
There is no need for the requirement for conditional-move comparison
operands to be stricter for T-Head targets than for other targets and
limit them to registers only. Constants will be reloaded if required
just as with branches or other-target conditional-move operations and
there is no extra overhead specific to the T-Head case. This enables
more opportunities for a branchless sequence to be produced.
gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Also
accept constants for T-Head comparison operands.
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e418ccc..ac2e76f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4126,8 +4126,8 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) && reg_or_0_operand (cons, mode) && reg_or_0_operand (alt, mode) && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode) - && GET_MODE (op0) == mode - && GET_MODE (op1) == mode + && (GET_MODE (op0) == mode || CONST_INT_P (op0)) + && (GET_MODE (op1) == mode || CONST_INT_P (op1)) && (code == EQ || code == NE)) need_eq_ne_p = true; |